This paper presents a low-power, high-speed two-stage dynamic latched comparator designed for high-resolution analog-to-digital converters (ADCs) using 22 nm FinFET technology. The comparator utilizes both CMOS and FinFET components, offering improved performance over bulk CMOS. The design addresses the limitations of traditional comparators by incorporating a cascode pre-amplifier to enhance differential gain and reduce input referred noise. A transconductance-enhanced latch stage is also used to improve performance. The comparator operates at a supply voltage of 0.8 V and a clock frequency of 1 GHz, achieving a delay of 50.42 ps, input referred noise of 190 μV, and an input offset voltage of 5.2 mV with a power consumption of 7.67 μW and a low power delay product (PDP) of 0.382 fJ. The FinFET-based comparator shows a 20.6% improvement in delay and 12.5% reduction in power dissipation compared to bulk CMOS-based comparators, and better PDP than conventional double tail pre-amplifier-based comparators. The active area of the comparator is 5.93 μm × 2.85 μm. The paper also discusses the advantages of FinFETs over planar MOSFETs, including better channel control, reduced short-channel effects, lower leakage current, and lower output conductance. The design is suitable for low-power, high-speed analog and mixed-signal circuits, particularly in portable applications where power consumption and noise are critical factors. The comparator's architecture is optimized for low supply voltage, with a focus on minimizing input referred noise and power dissipation while maintaining optimal offset voltage. The paper highlights the potential of FinFET technology in low-power analog and mixed-signal circuits, emphasizing its improved performance and suitability for advanced applications.This paper presents a low-power, high-speed two-stage dynamic latched comparator designed for high-resolution analog-to-digital converters (ADCs) using 22 nm FinFET technology. The comparator utilizes both CMOS and FinFET components, offering improved performance over bulk CMOS. The design addresses the limitations of traditional comparators by incorporating a cascode pre-amplifier to enhance differential gain and reduce input referred noise. A transconductance-enhanced latch stage is also used to improve performance. The comparator operates at a supply voltage of 0.8 V and a clock frequency of 1 GHz, achieving a delay of 50.42 ps, input referred noise of 190 μV, and an input offset voltage of 5.2 mV with a power consumption of 7.67 μW and a low power delay product (PDP) of 0.382 fJ. The FinFET-based comparator shows a 20.6% improvement in delay and 12.5% reduction in power dissipation compared to bulk CMOS-based comparators, and better PDP than conventional double tail pre-amplifier-based comparators. The active area of the comparator is 5.93 μm × 2.85 μm. The paper also discusses the advantages of FinFETs over planar MOSFETs, including better channel control, reduced short-channel effects, lower leakage current, and lower output conductance. The design is suitable for low-power, high-speed analog and mixed-signal circuits, particularly in portable applications where power consumption and noise are critical factors. The comparator's architecture is optimized for low supply voltage, with a focus on minimizing input referred noise and power dissipation while maintaining optimal offset voltage. The paper highlights the potential of FinFET technology in low-power analog and mixed-signal circuits, emphasizing its improved performance and suitability for advanced applications.