This paper proposes a 1500-A/48-V-to-1-V switching bus converter for next-generation ultra-high-power processors, such as GPUs, CPUs, and ASICs. The converter features a single-stage vertical power delivery (VPD) architecture, eliminating the need for dc bus capacitors and reducing the switch count. The proposed topology consists of two 2-to-1 switched-capacitor (SC) front-ends and four 10-branch series-capacitor-buck (SCB) modules, merged through four switching buses. This design reduces power conversion losses and improves overall system efficiency and power density. A hardware prototype was built with custom four-phase coupled inductors and gate drive daughterboards, achieving a peak system efficiency of 92.7%, full-load system efficiency of 85.7%, and power density of 759 W/in³ at 1500-A output current and 1-V output voltage. The prototype's performance surpasses that of existing 48-V-to-1-V solutions, demonstrating the potential for higher efficiency and power density. The paper also includes a detailed analysis of the hardware design, including the optimization of the four-phase coupled inductor and the development of a hybrid gate drive circuit to overcome the challenges of conventional cascaded bootstrapping.This paper proposes a 1500-A/48-V-to-1-V switching bus converter for next-generation ultra-high-power processors, such as GPUs, CPUs, and ASICs. The converter features a single-stage vertical power delivery (VPD) architecture, eliminating the need for dc bus capacitors and reducing the switch count. The proposed topology consists of two 2-to-1 switched-capacitor (SC) front-ends and four 10-branch series-capacitor-buck (SCB) modules, merged through four switching buses. This design reduces power conversion losses and improves overall system efficiency and power density. A hardware prototype was built with custom four-phase coupled inductors and gate drive daughterboards, achieving a peak system efficiency of 92.7%, full-load system efficiency of 85.7%, and power density of 759 W/in³ at 1500-A output current and 1-V output voltage. The prototype's performance surpasses that of existing 48-V-to-1-V solutions, demonstrating the potential for higher efficiency and power density. The paper also includes a detailed analysis of the hardware design, including the optimization of the four-phase coupled inductor and the development of a hybrid gate drive circuit to overcome the challenges of conventional cascaded bootstrapping.