This paper introduces a novel multi-expert large language model (MEV-LLM) architecture for generating Verilog code, addressing the limitations of existing approaches in generating syntactically and functionally correct code. The MEV-LLM integrates multiple LLMs, each fine-tuned with datasets categorized by design complexity, enabling more targeted learning and improved code generation. The architecture includes a complexity classifier to determine the appropriate expert model for a given task, and a categorized dataset to enhance fine-tuning effectiveness. The proposed method achieves up to 23.9% improvement in the pass@k metric compared to state-of-the-art models like CodeGen-Verilog and GEMMA. The dataset is enriched with detailed descriptions and categorized into four complexity levels: basic, intermediate, advanced, and expert. The study also evaluates the effectiveness of supervised fine-tuning, showing its superiority over unsupervised methods. The results demonstrate that the MEV-LLM significantly improves the quality of Verilog code generation, highlighting the potential of multi-expert architectures in automated hardware design. The paper also discusses the importance of dataset quality in fine-tuning and the benefits of using fine-grained labels. The proposed framework offers a promising approach for enhancing the accuracy and efficiency of hardware design through machine learning.This paper introduces a novel multi-expert large language model (MEV-LLM) architecture for generating Verilog code, addressing the limitations of existing approaches in generating syntactically and functionally correct code. The MEV-LLM integrates multiple LLMs, each fine-tuned with datasets categorized by design complexity, enabling more targeted learning and improved code generation. The architecture includes a complexity classifier to determine the appropriate expert model for a given task, and a categorized dataset to enhance fine-tuning effectiveness. The proposed method achieves up to 23.9% improvement in the pass@k metric compared to state-of-the-art models like CodeGen-Verilog and GEMMA. The dataset is enriched with detailed descriptions and categorized into four complexity levels: basic, intermediate, advanced, and expert. The study also evaluates the effectiveness of supervised fine-tuning, showing its superiority over unsupervised methods. The results demonstrate that the MEV-LLM significantly improves the quality of Verilog code generation, highlighting the potential of multi-expert architectures in automated hardware design. The paper also discusses the importance of dataset quality in fine-tuning and the benefits of using fine-grained labels. The proposed framework offers a promising approach for enhancing the accuracy and efficiency of hardware design through machine learning.