This paper introduces a novel multi-expert large language model (MEV-LLM) architecture for Verilog code generation, addressing the limitations of existing approaches in terms of code quality. The MEV-LLM integrates multiple LLMs, each fine-tuned for a specific level of design complexity, allowing for more targeted learning and improved generation of syntactically and functionally correct Verilog code. The architecture is evaluated using a categorized dataset, which is developed to enhance the effectiveness of LLM fine-tuning. Experiments show that the MEV-LLM improves the *pass@k* metric by up to 23.9% compared to state-of-the-art approaches, demonstrating its efficacy in automated hardware design through machine learning. The paper also discusses the importance of dataset quality and the impact of fine-grained labels on model performance.This paper introduces a novel multi-expert large language model (MEV-LLM) architecture for Verilog code generation, addressing the limitations of existing approaches in terms of code quality. The MEV-LLM integrates multiple LLMs, each fine-tuned for a specific level of design complexity, allowing for more targeted learning and improved generation of syntactically and functionally correct Verilog code. The architecture is evaluated using a categorized dataset, which is developed to enhance the effectiveness of LLM fine-tuning. Experiments show that the MEV-LLM improves the *pass@k* metric by up to 23.9% compared to state-of-the-art approaches, demonstrating its efficacy in automated hardware design through machine learning. The paper also discusses the importance of dataset quality and the impact of fine-grained labels on model performance.