This paper proposes an efficient algorithm for detecting unused integrated circuits (ICs) in parallel scan architecture. The algorithm aims to identify and differentiate between '0' and '1' states in a large SRAM memory array, thereby improving the efficiency of task distribution to unused ICs. The proposed method addresses the challenges of detecting unused SRAM in large memory arrays, which can lead to reduced lifetime and increased power dissipation. The algorithm is designed to avoid unbalanced '0' and '1' concentrations in the SRAM memory array and optimize the area required for the memory array. Simulation results show that the proposed method is more efficient in terms of reliability, detection rate, and power dissipation compared to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm. The algorithm utilizes the power-up state of flip-flops (FFs) in the scan architecture to detect reused ICs. The FFs are scanned for their power-up states, and the inherent asymmetry property of FFs is used to create two groups of FFs for 0 and 1 aging. The algorithm involves two phases: characterization and authentication. In the characterization phase, the power-up states of the FFs are analyzed to determine their aging characteristics. In the authentication phase, the power-up states of the FFs are used to determine whether an IC is reused or new. The algorithm calculates the percentage of logic 1s in each group and compares it to a threshold value to determine if the IC is reused. The proposed method has been validated through simulations using HSPICE and MOS reliability analysis. The results show that the proposed method is effective in detecting reused ICs, with improved performance in terms of reliability, accuracy, and power dissipation compared to conventional methods. The algorithm is capable of operating without any overheads in 128 bits and can be applied to highly integrated very large-scale integration (VLSI) chips. The method is also capable of supporting more parallel and switching operations due to the equal distribution of 1s and 0s in the entire SRAM memory array. The proposed method has potential for future applications in 64-bit operation and can enhance the scan of unused ICs in highly integrated VLSI chips.This paper proposes an efficient algorithm for detecting unused integrated circuits (ICs) in parallel scan architecture. The algorithm aims to identify and differentiate between '0' and '1' states in a large SRAM memory array, thereby improving the efficiency of task distribution to unused ICs. The proposed method addresses the challenges of detecting unused SRAM in large memory arrays, which can lead to reduced lifetime and increased power dissipation. The algorithm is designed to avoid unbalanced '0' and '1' concentrations in the SRAM memory array and optimize the area required for the memory array. Simulation results show that the proposed method is more efficient in terms of reliability, detection rate, and power dissipation compared to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm. The algorithm utilizes the power-up state of flip-flops (FFs) in the scan architecture to detect reused ICs. The FFs are scanned for their power-up states, and the inherent asymmetry property of FFs is used to create two groups of FFs for 0 and 1 aging. The algorithm involves two phases: characterization and authentication. In the characterization phase, the power-up states of the FFs are analyzed to determine their aging characteristics. In the authentication phase, the power-up states of the FFs are used to determine whether an IC is reused or new. The algorithm calculates the percentage of logic 1s in each group and compares it to a threshold value to determine if the IC is reused. The proposed method has been validated through simulations using HSPICE and MOS reliability analysis. The results show that the proposed method is effective in detecting reused ICs, with improved performance in terms of reliability, accuracy, and power dissipation compared to conventional methods. The algorithm is capable of operating without any overheads in 128 bits and can be applied to highly integrated very large-scale integration (VLSI) chips. The method is also capable of supporting more parallel and switching operations due to the equal distribution of 1s and 0s in the entire SRAM memory array. The proposed method has potential for future applications in 64-bit operation and can enhance the scan of unused ICs in highly integrated VLSI chips.