An efficient unused integrated circuits detection algorithm for parallel scan architecture

An efficient unused integrated circuits detection algorithm for parallel scan architecture

Vol. 14, No. 1, February 2024 | Rekha Sathyanarayana, Nataraj Kanathur Ramaswamy, Mallikarjunaswamy Srikantaswamy, Rekha Kanathur Ramaswamy
The paper presents an efficient algorithm for detecting unused integrated circuits (ICs) in parallel scan architecture, particularly in on-chip static random-access memory (SRAM) arrays. The authors, Rekha Sathyanarayana, Nataraj Kanathur Ramaswamy, Mallikarjunaswamy Srikanthaswamy, and Rekha Kanathur Ramaswamy, propose a method to differentiate between '0' and '1' states in large SRAM arrays, optimizing the distribution of tasks and reducing power dissipation. The algorithm avoids unbalancing the '0' and '1' concentrations and enhances the reliability and detection rate of both used and unused ICs compared to conventional methods like backscattering side-channel analysis (BSCA) and network-attached storage (NAS). The method leverages the symmetry property of SRAM cells and reduces thermal and electrical noise. The paper also discusses the modeling of flip-flop (FF) power-up states, the impact of process variations, and aging effects on FFs. The proposed method is validated through simulations using HSPICE, demonstrating improved performance in terms of reliability, detection rate, and power dissipation. The authors conclude that their method enhances the lifespan and reliability of ICs and supports more parallel and switching operations in SRAM arrays.The paper presents an efficient algorithm for detecting unused integrated circuits (ICs) in parallel scan architecture, particularly in on-chip static random-access memory (SRAM) arrays. The authors, Rekha Sathyanarayana, Nataraj Kanathur Ramaswamy, Mallikarjunaswamy Srikanthaswamy, and Rekha Kanathur Ramaswamy, propose a method to differentiate between '0' and '1' states in large SRAM arrays, optimizing the distribution of tasks and reducing power dissipation. The algorithm avoids unbalancing the '0' and '1' concentrations and enhances the reliability and detection rate of both used and unused ICs compared to conventional methods like backscattering side-channel analysis (BSCA) and network-attached storage (NAS). The method leverages the symmetry property of SRAM cells and reduces thermal and electrical noise. The paper also discusses the modeling of flip-flop (FF) power-up states, the impact of process variations, and aging effects on FFs. The proposed method is validated through simulations using HSPICE, demonstrating improved performance in terms of reliability, detection rate, and power dissipation. The authors conclude that their method enhances the lifespan and reliability of ICs and supports more parallel and switching operations in SRAM arrays.
Reach us at info@study.space