**BetterV: Controlled Verilog Generation with Discriminative Guidance** This paper introduces BetterV, a framework for generating Verilog code using large language models (LLMs). BetterV addresses the growing complexity of modern Integrated Circuits (ICs) by automating the circuit design process. The framework fine-tunes LLMs on processed domain-specific datasets and incorporates generative discriminators to guide the LLMs towards specific design demands. Key contributions include: 1. **Data Collection and Processing**: BetterV collects and processes Verilog modules from the internet to form a clean and abundant dataset. 2. **Instruct-Tuning**: Specialized methods are designed to fine-tune LLMs to understand Verilog knowledge, enhancing their ability to generate syntactically and functionally correct Verilog. 3. **Data Augmentation**: Augmented data is used to enrich the training set and train a generative discriminator, which guides the LLMs to optimize Verilog implementation. 4. **Generative Discriminator**: A generative discriminator is trained to guide the LLMs in generating or modifying Verilog implementations, reducing the number of iterations in industrial production. **Experiments and Results**: - **Functional Correctness**: BetterV outperforms GPT-4 on the VerilogEval benchmark, demonstrating its capability to generate correct Verilog. - **EDA Downstream Tasks**: BetterV achieves significant improvements on various EDA tasks, including synthesis node reduction and verification runtime reduction. - **Ablation Study**: The impact of the generative discriminator is evaluated, showing that it enhances both functional and syntactic correctness. **Discussion and Future Work**: - **Current Limitations**: BetterV faces challenges with closed-source models and computational overhead due to the need for token-level probabilities. - **Applicability to Other Domains**: The principles behind BetterV can be adapted to other domains with similar challenges, such as genomics and structured languages. BetterV represents a pioneering advancement in Verilog generation and EDA, offering a versatile solution for optimizing Verilog implementations and reducing the complexity of modern IC design.**BetterV: Controlled Verilog Generation with Discriminative Guidance** This paper introduces BetterV, a framework for generating Verilog code using large language models (LLMs). BetterV addresses the growing complexity of modern Integrated Circuits (ICs) by automating the circuit design process. The framework fine-tunes LLMs on processed domain-specific datasets and incorporates generative discriminators to guide the LLMs towards specific design demands. Key contributions include: 1. **Data Collection and Processing**: BetterV collects and processes Verilog modules from the internet to form a clean and abundant dataset. 2. **Instruct-Tuning**: Specialized methods are designed to fine-tune LLMs to understand Verilog knowledge, enhancing their ability to generate syntactically and functionally correct Verilog. 3. **Data Augmentation**: Augmented data is used to enrich the training set and train a generative discriminator, which guides the LLMs to optimize Verilog implementation. 4. **Generative Discriminator**: A generative discriminator is trained to guide the LLMs in generating or modifying Verilog implementations, reducing the number of iterations in industrial production. **Experiments and Results**: - **Functional Correctness**: BetterV outperforms GPT-4 on the VerilogEval benchmark, demonstrating its capability to generate correct Verilog. - **EDA Downstream Tasks**: BetterV achieves significant improvements on various EDA tasks, including synthesis node reduction and verification runtime reduction. - **Ablation Study**: The impact of the generative discriminator is evaluated, showing that it enhances both functional and syntactic correctness. **Discussion and Future Work**: - **Current Limitations**: BetterV faces challenges with closed-source models and computational overhead due to the need for token-level probabilities. - **Applicability to Other Domains**: The principles behind BetterV can be adapted to other domains with similar challenges, such as genomics and structured languages. BetterV represents a pioneering advancement in Verilog generation and EDA, offering a versatile solution for optimizing Verilog implementations and reducing the complexity of modern IC design.