This paper explores the limits of multicore scaling in the context of power constraints, a critical issue that may soon limit the continued growth in core counts. The authors model multicore scaling by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads over the next five technology generations. They use both ITRS projections and conservative device scaling parameters to model device scaling, and they derive Pareto-optimal frontiers for area/performance and power/performance from measurements of over 150 processors to model single-core scaling. For multicore scaling, they build a detailed performance model that considers upper-bound performance and lower-bound core power. The study examines various multicore designs, including single-threaded CPU-like and massively threaded GPU-like multicore chip organizations with different topologies. The results show that multicore scaling is power-limited, with 21% of a fixed-size chip being powered off at 22 nm and over 50% at 8 nm. By 2024, only a 7.9× average speedup is possible across commonly used parallel workloads, highlighting a significant gap between expected and achievable performance. The paper also discusses the limitations of current multicore designs and suggests that radical microarchitectural innovations are necessary to achieve the expected performance improvements.This paper explores the limits of multicore scaling in the context of power constraints, a critical issue that may soon limit the continued growth in core counts. The authors model multicore scaling by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads over the next five technology generations. They use both ITRS projections and conservative device scaling parameters to model device scaling, and they derive Pareto-optimal frontiers for area/performance and power/performance from measurements of over 150 processors to model single-core scaling. For multicore scaling, they build a detailed performance model that considers upper-bound performance and lower-bound core power. The study examines various multicore designs, including single-threaded CPU-like and massively threaded GPU-like multicore chip organizations with different topologies. The results show that multicore scaling is power-limited, with 21% of a fixed-size chip being powered off at 22 nm and over 50% at 8 nm. By 2024, only a 7.9× average speedup is possible across commonly used parallel workloads, highlighting a significant gap between expected and achievable performance. The paper also discusses the limitations of current multicore designs and suggests that radical microarchitectural innovations are necessary to achieve the expected performance improvements.