This paper presents the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits with dimensions of about 1 micrometer. The study focuses on scaling relationships that allow conventional MOSFETs to be reduced in size. An improved device structure is introduced that uses ion implantation to create shallow source and drain regions and a non-uniform substrate doping profile. One-dimensional models predict the substrate doping profile and threshold voltage characteristics, while a two-dimensional current transport model predicts short-channel effects. Polysilicon-gate MOSFETs with channel lengths as short as 0.5 micrometers were fabricated and tested. The paper discusses the performance improvements expected from using these small devices in highly miniaturized circuits. The paper also explores the use of ion implantation to improve device design. Ion implantation allows for controlled doping, reducing threshold voltage sensitivity to source-to-substrate bias. This enables the use of a thicker gate insulator, which is easier to fabricate. Shallow source and drain regions formed by ion implantation reduce short-channel effects while maintaining acceptable sheet resistance. The combination of these features in an all-implanted design results in a device with well-controlled threshold characteristics and reduced inter-electrode capacitance. The paper describes the scaling principles applied to a conventional MOSFET to achieve a small device structure. Experimental verification of the scaling approach is presented, followed by a description of the fabrication process for the improved scaled-down device using ion implantation. Design considerations are based on analytical tools: a one-dimensional model predicting substrate sensitivity and a two-dimensional model predicting turn-on characteristics. Predicted results are compared with experimental data. The paper also discusses an alternate design for zero substrate bias, which offers advantages in threshold control. The paper concludes with a discussion of the performance improvements expected from using these very small FETs in integrated circuits. The study highlights the importance of ion implantation in overcoming challenges associated with scaling down MOSFETs, leading to improved performance and reliability in highly miniaturized circuits.This paper presents the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits with dimensions of about 1 micrometer. The study focuses on scaling relationships that allow conventional MOSFETs to be reduced in size. An improved device structure is introduced that uses ion implantation to create shallow source and drain regions and a non-uniform substrate doping profile. One-dimensional models predict the substrate doping profile and threshold voltage characteristics, while a two-dimensional current transport model predicts short-channel effects. Polysilicon-gate MOSFETs with channel lengths as short as 0.5 micrometers were fabricated and tested. The paper discusses the performance improvements expected from using these small devices in highly miniaturized circuits. The paper also explores the use of ion implantation to improve device design. Ion implantation allows for controlled doping, reducing threshold voltage sensitivity to source-to-substrate bias. This enables the use of a thicker gate insulator, which is easier to fabricate. Shallow source and drain regions formed by ion implantation reduce short-channel effects while maintaining acceptable sheet resistance. The combination of these features in an all-implanted design results in a device with well-controlled threshold characteristics and reduced inter-electrode capacitance. The paper describes the scaling principles applied to a conventional MOSFET to achieve a small device structure. Experimental verification of the scaling approach is presented, followed by a description of the fabrication process for the improved scaled-down device using ion implantation. Design considerations are based on analytical tools: a one-dimensional model predicting substrate sensitivity and a two-dimensional model predicting turn-on characteristics. Predicted results are compared with experimental data. The paper also discusses an alternate design for zero substrate bias, which offers advantages in threshold control. The paper concludes with a discussion of the performance improvements expected from using these very small FETs in integrated circuits. The study highlights the importance of ion implantation in overcoming challenges associated with scaling down MOSFETs, leading to improved performance and reliability in highly miniaturized circuits.