Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions

Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions

VOL. 87, NO. 4, APRIL 1999 | ROBERT H. DENNARD, MEMBER, IEEE, FRITZ H. GAENSSLEN, HWA-NIEN YU, MEMBER, IEEE, V. LEO RIDEOUT, MEMBER, IEEE, ERNEST BASSOUS, AND ANDRE R. LEBLANC, MEMBER, IEEE
This paper discusses the design, fabrication, and characterization of very small MOSFETs suitable for digital integrated circuits, with dimensions on the order of 1 μm. The authors present scaling relationships to reduce conventional MOSFETs to smaller sizes while maintaining performance. They introduce an improved design using ion implantation to create shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional and two-dimensional models are used to predict substrate doping profiles, threshold voltage, and short-channel effects. Polysilicon-gate MOSFETs with channel lengths as short as 0.5 μm were fabricated and tested, showing good agreement with predicted characteristics. The paper also explores an alternate design for zero substrate bias, which offers advantages in threshold control but has a higher subthreshold turn-on range. The performance improvements expected from using these small MOSFETs in highly miniaturized integrated circuits are discussed, highlighting the benefits in terms of reduced capacitance, delay time, and power dissipation.This paper discusses the design, fabrication, and characterization of very small MOSFETs suitable for digital integrated circuits, with dimensions on the order of 1 μm. The authors present scaling relationships to reduce conventional MOSFETs to smaller sizes while maintaining performance. They introduce an improved design using ion implantation to create shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional and two-dimensional models are used to predict substrate doping profiles, threshold voltage, and short-channel effects. Polysilicon-gate MOSFETs with channel lengths as short as 0.5 μm were fabricated and tested, showing good agreement with predicted characteristics. The paper also explores an alternate design for zero substrate bias, which offers advantages in threshold control but has a higher subthreshold turn-on range. The performance improvements expected from using these small MOSFETs in highly miniaturized integrated circuits are discussed, highlighting the benefits in terms of reduced capacitance, delay time, and power dissipation.
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