Design Issues in CMOS Differential LC Oscillators

Design Issues in CMOS Differential LC Oscillators

May 1999 | Ali Hajimiri and Thomas H. Lee
The paper by Ali Hajimiri and Thomas H. Lee analyzes phase noise in differential cross-coupled inductance–capacitance (LC) oscillators, focusing on the impact of tail current and tank power dissipation on voltage amplitude. The authors identify various noise sources in the complementary cross-coupled pair and their effects on phase noise, demonstrating good agreement between predictions and measurements over a wide range of tail currents and supply voltages. A 1.8-GHz LC oscillator is demonstrated, achieving a phase noise of −121 dBc/Hz at 600 kHz while dissipating only 6 mW of power using on-chip spiral inductors. The analysis covers the dependence of tank amplitude on tail current and supply voltage, the effect of noise sources in active and resistive tank loss, and the impact of tail-current noise. Experimental results and design insights are provided, highlighting the trade-offs between phase noise and power dissipation. The complementary structure is shown to offer superior performance over all-NMOS structures due to higher transconductance and better symmetry.The paper by Ali Hajimiri and Thomas H. Lee analyzes phase noise in differential cross-coupled inductance–capacitance (LC) oscillators, focusing on the impact of tail current and tank power dissipation on voltage amplitude. The authors identify various noise sources in the complementary cross-coupled pair and their effects on phase noise, demonstrating good agreement between predictions and measurements over a wide range of tail currents and supply voltages. A 1.8-GHz LC oscillator is demonstrated, achieving a phase noise of −121 dBc/Hz at 600 kHz while dissipating only 6 mW of power using on-chip spiral inductors. The analysis covers the dependence of tank amplitude on tail current and supply voltage, the effect of noise sources in active and resistive tank loss, and the impact of tail-current noise. Experimental results and design insights are provided, highlighting the trade-offs between phase noise and power dissipation. The complementary structure is shown to offer superior performance over all-NMOS structures due to higher transconductance and better symmetry.
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