The paper presents an algorithm for dividing a graph into triconnected components, which are subgraphs where no vertex can be removed without disconnecting the graph. The algorithm is implemented on a random-access computer and requires O(V+E) time and space, where V is the number of vertices and E is the number of edges. The method uses depth-first search (DFS) to explore the graph and identify separation pairs, which are pairs of vertices whose removal would disconnect the graph. The algorithm first finds cycles in the graph and then determines the segments formed by deleting these cycles. It then recursively tests each segment for separation pairs and merges the segments to form triconnected components. The key steps involve calculating LOWPT values, constructing an acceptable adjacency structure, and performing DFS to generate paths. The algorithm is theoretically optimal and efficient in practice, making it useful for various applications such as analyzing electrical circuits, determining planarity, and testing isomorphism of planar graphs.The paper presents an algorithm for dividing a graph into triconnected components, which are subgraphs where no vertex can be removed without disconnecting the graph. The algorithm is implemented on a random-access computer and requires O(V+E) time and space, where V is the number of vertices and E is the number of edges. The method uses depth-first search (DFS) to explore the graph and identify separation pairs, which are pairs of vertices whose removal would disconnect the graph. The algorithm first finds cycles in the graph and then determines the segments formed by deleting these cycles. It then recursively tests each segment for separation pairs and merges the segments to form triconnected components. The key steps involve calculating LOWPT values, constructing an acceptable adjacency structure, and performing DFS to generate paths. The algorithm is theoretically optimal and efficient in practice, making it useful for various applications such as analyzing electrical circuits, determining planarity, and testing isomorphism of planar graphs.