This paper presents a distributed Union-Find (UF) decoder for surface codes, implemented on an FPGA called Helios. The decoder achieves sublinear average time complexity with respect to the code distance d, using O(d³) parallel computing resources. The implementation is scalable and efficient, with a hybrid tree-grid structure that allows for customizable trade-offs between latency and resource usage. The decoder is tested on a Xilinx VCU129 FPGA, achieving decoding times of 11.5 ns for d = 21 under 0.1% phenomenological noise and 544 ns for d = 51 under p = 0.001 phenomenological noise. The results show that the decoder is significantly faster than existing implementations and can scale to arbitrarily large surface codes without increasing the backlog. The decoder is also shown to be able to decode surface codes with erasure errors, weighted edges, and sliding-window decoding. The implementation is open-source and available for further development.This paper presents a distributed Union-Find (UF) decoder for surface codes, implemented on an FPGA called Helios. The decoder achieves sublinear average time complexity with respect to the code distance d, using O(d³) parallel computing resources. The implementation is scalable and efficient, with a hybrid tree-grid structure that allows for customizable trade-offs between latency and resource usage. The decoder is tested on a Xilinx VCU129 FPGA, achieving decoding times of 11.5 ns for d = 21 under 0.1% phenomenological noise and 544 ns for d = 51 under p = 0.001 phenomenological noise. The results show that the decoder is significantly faster than existing implementations and can scale to arbitrarily large surface codes without increasing the backlog. The decoder is also shown to be able to decode surface codes with erasure errors, weighted edges, and sliding-window decoding. The implementation is open-source and available for further development.