The paper presents a distributed Union-Find (UF) decoder for surface codes, which is designed to exploit parallel computing resources to achieve faster error correction in quantum computers. The UF decoder has an average time complexity slightly higher than \(O(d^3)\), but the distributed version, implemented using an FPGA-based architecture called Helios, demonstrates sublinear average time complexity with respect to \(d\). Helios organizes parallel computing resources into a hybrid tree-grid structure, allowing for scalable and efficient decoding. The implementation on a Xilinx VCU129 FPGA successfully decodes surface codes up to \(d = 21\) with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise, and up to \(d = 17\) with an average decoding time of 23.7 ns under equivalent circuit-level noise. The paper also shows that Helios can optimize resource usage by decoding \(d = 51\) on the same FPGA with an average latency of 544 ns per measurement round. The contributions include a distributed UF decoder, the Helios architecture, empirical data demonstrating decreasing decoding time per round as \(d\) increases, and the ability to trade-off resource usage for latency.The paper presents a distributed Union-Find (UF) decoder for surface codes, which is designed to exploit parallel computing resources to achieve faster error correction in quantum computers. The UF decoder has an average time complexity slightly higher than \(O(d^3)\), but the distributed version, implemented using an FPGA-based architecture called Helios, demonstrates sublinear average time complexity with respect to \(d\). Helios organizes parallel computing resources into a hybrid tree-grid structure, allowing for scalable and efficient decoding. The implementation on a Xilinx VCU129 FPGA successfully decodes surface codes up to \(d = 21\) with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise, and up to \(d = 17\) with an average decoding time of 23.7 ns under equivalent circuit-level noise. The paper also shows that Helios can optimize resource usage by decoding \(d = 51\) on the same FPGA with an average latency of 544 ns per measurement round. The contributions include a distributed UF decoder, the Helios architecture, empirical data demonstrating decreasing decoding time per round as \(d\) increases, and the ability to trade-off resource usage for latency.