This paper presents RMT (Reconfigurable Match Tables), a new architecture for switching chips that allows flexible and efficient packet processing in Software Defined Networking (SDN). RMT is a RISC-inspired pipelined architecture that enables the forwarding plane to be reconfigured in the field without modifying hardware. The RMT model allows the programmer to specify multiple match tables of arbitrary width and depth, with each table configurable for matching on arbitrary fields. RMT allows the programmer to modify all header fields much more comprehensively than in OpenFlow. The paper describes the design of a 64-port by 10 Gb/s switch chip implementing the RMT model. The chip design demonstrates that flexible OpenFlow hardware switch implementations are feasible at almost no additional cost or power. The RMT model allows new fields to be added by modifying the parser, new fields to be matched by modifying match memories, new actions by modifying stage instructions, and new queueing by modifying the queue discipline for each queue. An ideal RMT can simulate existing devices such as a bridge, a router, or a firewall; and can implement existing protocols, such as MPLS and ECN, and protocols proposed in the literature, such as RCP that uses non-standard congestion fields. Most importantly, it allows future data plane modifications without modifying hardware. The RMT architecture is implemented with a large number of physical pipeline stages that a smaller number of logical RMT stages can be mapped to, depending on the resource needs of each logical stage. The implementation architecture is motivated by factoring state, flexible resource allocation minimizing resource waste, and layout optimality. The physical pipeline stage architecture needs restrictions to allow terabit-speed realization. Match restrictions, packet header limits, memory restrictions, and action restrictions are all considered in the design. The paper also presents example use cases, including an L2/L3 switch and RCP and ACL support. The RMT model is shown to be flexible and efficient, allowing for a wide range of packet processing tasks. The paper concludes that RMT is a good way to think about programming the network and lends itself to direct expression in hardware using a configurable pipeline of match tables and action processors. The RMT model is also shown to be cost-competitive with fixed designs, with flexibility coming at almost no cost.This paper presents RMT (Reconfigurable Match Tables), a new architecture for switching chips that allows flexible and efficient packet processing in Software Defined Networking (SDN). RMT is a RISC-inspired pipelined architecture that enables the forwarding plane to be reconfigured in the field without modifying hardware. The RMT model allows the programmer to specify multiple match tables of arbitrary width and depth, with each table configurable for matching on arbitrary fields. RMT allows the programmer to modify all header fields much more comprehensively than in OpenFlow. The paper describes the design of a 64-port by 10 Gb/s switch chip implementing the RMT model. The chip design demonstrates that flexible OpenFlow hardware switch implementations are feasible at almost no additional cost or power. The RMT model allows new fields to be added by modifying the parser, new fields to be matched by modifying match memories, new actions by modifying stage instructions, and new queueing by modifying the queue discipline for each queue. An ideal RMT can simulate existing devices such as a bridge, a router, or a firewall; and can implement existing protocols, such as MPLS and ECN, and protocols proposed in the literature, such as RCP that uses non-standard congestion fields. Most importantly, it allows future data plane modifications without modifying hardware. The RMT architecture is implemented with a large number of physical pipeline stages that a smaller number of logical RMT stages can be mapped to, depending on the resource needs of each logical stage. The implementation architecture is motivated by factoring state, flexible resource allocation minimizing resource waste, and layout optimality. The physical pipeline stage architecture needs restrictions to allow terabit-speed realization. Match restrictions, packet header limits, memory restrictions, and action restrictions are all considered in the design. The paper also presents example use cases, including an L2/L3 switch and RCP and ACL support. The RMT model is shown to be flexible and efficient, allowing for a wide range of packet processing tasks. The paper concludes that RMT is a good way to think about programming the network and lends itself to direct expression in hardware using a configurable pipeline of match tables and action processors. The RMT model is also shown to be cost-competitive with fixed designs, with flexibility coming at almost no cost.