Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN

Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN

August 12–16, 2013, Hong Kong, China | Pat Bosshart†, Glen Gibb†, Hun-Seok Kim†, George Varghese§, Nick McKeown†, Martin Izzard†, Fernando Mujica†, Mark Horowitz†
This paper addresses the limitations of current switching chips and the OpenFlow protocol in Software Defined Networking (SDN) by proposing the RMT (Reconfigurable Match Tables) model. RMT is a new RISC-inspired pipelined architecture for switching chips that allows the forwarding plane to be changed in the field without modifying hardware. The authors describe a 64-port, 10 Gb/s switch chip implementing the RMT model, demonstrating that flexible OpenFlow hardware switch implementations are feasible at almost no additional cost or power. The RMT model allows the forwarding plane to be reconfigured in four ways: altering field definitions, specifying the number and topology of match tables, defining new actions, and placing modified packets in specified queues. The paper includes detailed design and implementation details, including a configurable parser, match memories, and action engine. The evaluation shows that the increased area and power for configurability are minimal compared to conventional switch chips.This paper addresses the limitations of current switching chips and the OpenFlow protocol in Software Defined Networking (SDN) by proposing the RMT (Reconfigurable Match Tables) model. RMT is a new RISC-inspired pipelined architecture for switching chips that allows the forwarding plane to be changed in the field without modifying hardware. The authors describe a 64-port, 10 Gb/s switch chip implementing the RMT model, demonstrating that flexible OpenFlow hardware switch implementations are feasible at almost no additional cost or power. The RMT model allows the forwarding plane to be reconfigured in four ways: altering field definitions, specifying the number and topology of match tables, defining new actions, and placing modified packets in specified queues. The paper includes detailed design and implementation details, including a configurable parser, match memories, and action engine. The evaluation shows that the increased area and power for configurability are minimal compared to conventional switch chips.
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