This paper demonstrates that commercial off-the-shelf (COTS) DRAM chips can perform functionally complete Boolean operations, including NOT, NAND, and NOR, as well as many-input (more than two inputs) AND and OR operations. The authors experimentally characterize these operations on 256 modern DDR4 DRAM chips from 22 modules, focusing on SK Hynix and Samsung chips. They evaluate the reliability of these operations using a success rate metric, which measures the fraction of correctly performed bitwise operations. Key findings include: 1. **NOT Operation**: COTS DRAM chips can perform the NOT operation with an average success rate of 98.37%. 2. **Many-Input NAND, NOR, AND, and OR Operations**: These operations can be performed with up to 16 inputs, achieving high reliability (success rates of 94.94%, 95.87%, 94.94%, and 95.85%, respectively). 3. **Data Pattern Impact**: The success rate of NAND, NOR, AND, and OR operations is slightly affected by data patterns, with random patterns leading to a decrease in success rate by 1.39%, 1.97%, 1.43%, and 1.98%, respectively. 4. **Temperature Resilience**: These operations are highly resilient to temperature changes, with a maximum success rate fluctuation of only 1.66% when the temperature increases from 50°C to 95°C. The authors hypothesize that these capabilities arise from the analog operational properties of DRAM circuitry, particularly the hierarchical design of row decoder circuitry and the shared sense amplifiers in neighboring subarrays. They provide a detailed methodology for performing simultaneous multiple-row activation and analyze the impact of various factors on the reliability of these operations. The results fill a gap in understanding the computational capabilities of COTS DRAM chips and demonstrate the potential of using DRAM as a powerful computation substrate.This paper demonstrates that commercial off-the-shelf (COTS) DRAM chips can perform functionally complete Boolean operations, including NOT, NAND, and NOR, as well as many-input (more than two inputs) AND and OR operations. The authors experimentally characterize these operations on 256 modern DDR4 DRAM chips from 22 modules, focusing on SK Hynix and Samsung chips. They evaluate the reliability of these operations using a success rate metric, which measures the fraction of correctly performed bitwise operations. Key findings include: 1. **NOT Operation**: COTS DRAM chips can perform the NOT operation with an average success rate of 98.37%. 2. **Many-Input NAND, NOR, AND, and OR Operations**: These operations can be performed with up to 16 inputs, achieving high reliability (success rates of 94.94%, 95.87%, 94.94%, and 95.85%, respectively). 3. **Data Pattern Impact**: The success rate of NAND, NOR, AND, and OR operations is slightly affected by data patterns, with random patterns leading to a decrease in success rate by 1.39%, 1.97%, 1.43%, and 1.98%, respectively. 4. **Temperature Resilience**: These operations are highly resilient to temperature changes, with a maximum success rate fluctuation of only 1.66% when the temperature increases from 50°C to 95°C. The authors hypothesize that these capabilities arise from the analog operational properties of DRAM circuitry, particularly the hierarchical design of row decoder circuitry and the shared sense amplifiers in neighboring subarrays. They provide a detailed methodology for performing simultaneous multiple-row activation and analyze the impact of various factors on the reliability of these operations. The results fill a gap in understanding the computational capabilities of COTS DRAM chips and demonstrate the potential of using DRAM as a powerful computation substrate.