This paper presents experimental results showing that commercial off-the-shelf (COTS) DRAM chips can perform functionally-complete Boolean operations and many-input bitwise operations. The study demonstrates that COTS DDR4 DRAM chips can execute NOT, NAND, NOR, AND, and OR operations with high reliability. The researchers tested 256 COTS DDR4 DRAM chips from 22 modules and found that the average success rate for NOT operations is 98.37%, while for 16-input NAND, NOR, AND, and OR operations, the success rates are 94.94%, 95.87%, 94.94%, and 95.85%, respectively. The results show that data pattern and temperature variations have minimal impact on the success rate of these operations. The study also highlights that COTS DRAM chips are highly resilient to temperature changes, with success rate fluctuations of at most 1.66% when temperature increases from 50°C to 95°C. The researchers propose two hypotheses to explain how COTS DRAM chips can perform these operations, based on the open-bitline architecture and the operation of sense amplifiers. The study provides a detailed characterization of the reliability of these operations across different data patterns and temperatures, and opens-source their infrastructure for future research. The findings demonstrate the potential of using DRAM as a computation substrate and highlight the importance of understanding the computational capabilities of COTS DRAM chips.This paper presents experimental results showing that commercial off-the-shelf (COTS) DRAM chips can perform functionally-complete Boolean operations and many-input bitwise operations. The study demonstrates that COTS DDR4 DRAM chips can execute NOT, NAND, NOR, AND, and OR operations with high reliability. The researchers tested 256 COTS DDR4 DRAM chips from 22 modules and found that the average success rate for NOT operations is 98.37%, while for 16-input NAND, NOR, AND, and OR operations, the success rates are 94.94%, 95.87%, 94.94%, and 95.85%, respectively. The results show that data pattern and temperature variations have minimal impact on the success rate of these operations. The study also highlights that COTS DRAM chips are highly resilient to temperature changes, with success rate fluctuations of at most 1.66% when temperature increases from 50°C to 95°C. The researchers propose two hypotheses to explain how COTS DRAM chips can perform these operations, based on the open-bitline architecture and the operation of sense amplifiers. The study provides a detailed characterization of the reliability of these operations across different data patterns and temperatures, and opens-source their infrastructure for future research. The findings demonstrate the potential of using DRAM as a computation substrate and highlight the importance of understanding the computational capabilities of COTS DRAM chips.