This paper presents an integrated architectural and circuit-level approach to reduce leakage energy dissipation in deep-submicron cache memories. The key technique proposed is "gated-Vdd," a circuit-level method that gates the supply voltage to unused SRAM cells in a dynamically resizable instruction cache (DRI i-cache), thereby reducing leakage. The DRI i-cache dynamically adjusts its size based on application needs, minimizing cache utilization and leakage energy. Gated-Vdd enables the cache to turn off unused sections, significantly reducing leakage energy. The paper evaluates various circuit techniques for gated-Vdd, including NMOS and PMOS transistors, and finds that a wide NMOS dual-Vt gated-Vdd transistor with a charge pump provides the best performance, reducing leakage with minimal impact on cell speed and area. Experimental results show that a DRI i-cache with gated-Vdd reduces energy-delay by 62% with minimal impact on performance. The paper also discusses the trade-offs between leakage reduction, performance, and area overhead for different gated-Vdd techniques. Overall, the DRI i-cache significantly reduces leakage energy while maintaining high performance, making it an effective solution for energy-efficient deep-submicron cache memories.This paper presents an integrated architectural and circuit-level approach to reduce leakage energy dissipation in deep-submicron cache memories. The key technique proposed is "gated-Vdd," a circuit-level method that gates the supply voltage to unused SRAM cells in a dynamically resizable instruction cache (DRI i-cache), thereby reducing leakage. The DRI i-cache dynamically adjusts its size based on application needs, minimizing cache utilization and leakage energy. Gated-Vdd enables the cache to turn off unused sections, significantly reducing leakage energy. The paper evaluates various circuit techniques for gated-Vdd, including NMOS and PMOS transistors, and finds that a wide NMOS dual-Vt gated-Vdd transistor with a charge pump provides the best performance, reducing leakage with minimal impact on cell speed and area. Experimental results show that a DRI i-cache with gated-Vdd reduces energy-delay by 62% with minimal impact on performance. The paper also discusses the trade-offs between leakage reduction, performance, and area overhead for different gated-Vdd techniques. Overall, the DRI i-cache significantly reduces leakage energy while maintaining high performance, making it an effective solution for energy-efficient deep-submicron cache memories.