This paper introduces a novel circuit technique called gated-Vdd to reduce leakage energy dissipation in deep-submicron cache memories. The authors propose a dynamically resizable instruction-cache (DRI i-cache) architecture that dynamically adjusts the cache size based on application requirements, thereby reducing the number of active SRAM cells and minimizing leakage. The gated-Vdd technique gates the supply voltage to these unused cells, significantly reducing leakage without affecting performance. The paper evaluates various gated-Vdd configurations, finding that a wide NMOS dual-Vt gated-Vdd with a charge pump offers the best balance of leakage reduction, performance, and area overhead. Experimental results show that a 64K DRI i-cache reduces energy-delay by 62% with minimal impact on execution time.This paper introduces a novel circuit technique called gated-Vdd to reduce leakage energy dissipation in deep-submicron cache memories. The authors propose a dynamically resizable instruction-cache (DRI i-cache) architecture that dynamically adjusts the cache size based on application requirements, thereby reducing the number of active SRAM cells and minimizing leakage. The gated-Vdd technique gates the supply voltage to these unused cells, significantly reducing leakage without affecting performance. The paper evaluates various gated-Vdd configurations, finding that a wide NMOS dual-Vt gated-Vdd with a charge pump offers the best balance of leakage reduction, performance, and area overhead. Experimental results show that a 64K DRI i-cache reduces energy-delay by 62% with minimal impact on execution time.