This paper introduces HDLdebugger, an LLM-assisted framework for streamlining HDL debugging in chip design. HDLdebugger consists of three main components: data generation, a search engine, and retrieval-augmented LLM fine-tuning. The data generation process uses reverse engineering to create a diverse set of buggy HDL codes and their corresponding error messages. The search engine retrieves relevant information from HDL documents and code instances to enhance LLM performance. The retrieval-augmented LLM fine-tuning approach integrates self-guided thought generation and RAG-based fine-tuning to improve LLMs' ability to understand and repair HDL code. Extensive experiments on a Huawei HDL code dataset show that HDLdebugger outperforms 13 state-of-the-art baselines, including GPT4 and various LLMs, achieving a pass rate of up to 81.93%. The framework demonstrates significant improvements in HDL debugging efficiency and effectiveness.This paper introduces HDLdebugger, an LLM-assisted framework for streamlining HDL debugging in chip design. HDLdebugger consists of three main components: data generation, a search engine, and retrieval-augmented LLM fine-tuning. The data generation process uses reverse engineering to create a diverse set of buggy HDL codes and their corresponding error messages. The search engine retrieves relevant information from HDL documents and code instances to enhance LLM performance. The retrieval-augmented LLM fine-tuning approach integrates self-guided thought generation and RAG-based fine-tuning to improve LLMs' ability to understand and repair HDL code. Extensive experiments on a Huawei HDL code dataset show that HDLdebugger outperforms 13 state-of-the-art baselines, including GPT4 and various LLMs, achieving a pass rate of up to 81.93%. The framework demonstrates significant improvements in HDL debugging efficiency and effectiveness.