This review article discusses the hardware implementation of memristor-based artificial neural networks (ANNs), focusing on their potential to improve energy efficiency and computational throughput. Memristors, a novel technology beyond complementary metal-oxide-semiconductor (CMOS), are promising for memory devices due to their ability to store and compute with a small, massively-parallel footprint at low power. The article reviews the latest efforts in achieving hardware-based memristive ANNs, detailing the working principles of each block and different design alternatives, along with the tools required for accurate performance estimation. It aims to provide a comprehensive protocol for materials and methods involved in memristive neural networks for researchers and experts. The development of sophisticated ANNs is a priority for technological companies and governments, as they can boost the fabrication of AI systems that generate economic and social benefits. ANNs can compute and store large amounts of electronic data and execute complex operations. Examples include biometric pattern recognition in smartphones and online banking apps, object identification in images from social networks and security cameras, speech-to-text conversion, natural language processing, and online shopping recommendations. ANNs are implemented via software in general-purpose computing systems based on a central processing unit (CPU) and memory, the Von Neumann architecture. However, this architecture is inefficient due to continuous data exchange between units. GPUs and FPGAs are used to accelerate ANNs, but they consume more energy. ASICs based on CMOS technology can compute and store information in the same unit, allowing for fast parallel operations. The article discusses the challenges of fully-CMOS implementations of ANNs, which require many devices to simulate each synapse, threatening energy and area efficiency. Memristive devices can emulate synapses, accelerating computational tasks while reducing power consumption and footprint. Memristive devices can have multiple non-volatile states, low energy consumption, and scalable structures suitable for matrix integration. Recent studies have proposed using memristive devices to emulate synapses, accelerating ANN computational tasks while reducing power consumption. Memristive devices can have multiple non-volatile states, low energy consumption, and scalable structures suitable for matrix integration. The article reviews the latest efforts in achieving hardware-based memristive ANNs, detailing the working principles of each block and different design alternatives, along with the tools required for accurate performance estimation. It aims to provide a comprehensive protocol for materials and methods involved in memristive neural networks for researchers and experts.This review article discusses the hardware implementation of memristor-based artificial neural networks (ANNs), focusing on their potential to improve energy efficiency and computational throughput. Memristors, a novel technology beyond complementary metal-oxide-semiconductor (CMOS), are promising for memory devices due to their ability to store and compute with a small, massively-parallel footprint at low power. The article reviews the latest efforts in achieving hardware-based memristive ANNs, detailing the working principles of each block and different design alternatives, along with the tools required for accurate performance estimation. It aims to provide a comprehensive protocol for materials and methods involved in memristive neural networks for researchers and experts. The development of sophisticated ANNs is a priority for technological companies and governments, as they can boost the fabrication of AI systems that generate economic and social benefits. ANNs can compute and store large amounts of electronic data and execute complex operations. Examples include biometric pattern recognition in smartphones and online banking apps, object identification in images from social networks and security cameras, speech-to-text conversion, natural language processing, and online shopping recommendations. ANNs are implemented via software in general-purpose computing systems based on a central processing unit (CPU) and memory, the Von Neumann architecture. However, this architecture is inefficient due to continuous data exchange between units. GPUs and FPGAs are used to accelerate ANNs, but they consume more energy. ASICs based on CMOS technology can compute and store information in the same unit, allowing for fast parallel operations. The article discusses the challenges of fully-CMOS implementations of ANNs, which require many devices to simulate each synapse, threatening energy and area efficiency. Memristive devices can emulate synapses, accelerating computational tasks while reducing power consumption and footprint. Memristive devices can have multiple non-volatile states, low energy consumption, and scalable structures suitable for matrix integration. Recent studies have proposed using memristive devices to emulate synapses, accelerating ANN computational tasks while reducing power consumption. Memristive devices can have multiple non-volatile states, low energy consumption, and scalable structures suitable for matrix integration. The article reviews the latest efforts in achieving hardware-based memristive ANNs, detailing the working principles of each block and different design alternatives, along with the tools required for accurate performance estimation. It aims to provide a comprehensive protocol for materials and methods involved in memristive neural networks for researchers and experts.