The article discusses the development and performance of Universal Chiplet Interconnect Express (UCle) 1.0, an open industry standard interconnect for chiplet ecosystems. UCle 1.0 supports interoperability using standard and advanced packaging technologies with planar interconnects. The authors examine how UCle can evolve as bump interconnect pitches reduce with advances in packaging technologies for three-dimensional (3D) integration of chiplets. They report a die-to-die solution for package bump pitches down to 1 μm, providing circuit architecture details and performance results. The analysis suggests that reducing the frequency as the bump pitch decreases can achieve the most power-efficient performance. The proposed architectural approach offers power, performance, and reliability characteristics comparable to or exceeding those of monolithic system-on-chip designs as the bump pitch approaches 1 μm. UCle 1.0 defines two types of packaging: standard (UCle-S) and advanced (UCle-A). The standard package is cost-effective, while the advanced package is power-efficient. UCle supports different data rates, widths, bump pitches, and channel reach to ensure interoperability. The physical layer (PHY) handles electrical signaling, clocking, link training, and circuit architecture. The basic unit is a module comprising multiple data lanes, validation and tracking lanes, and a differential forwarded-clock per direction. The authors propose a next-generation UCle, referred to as UCle-3D, which is unidirectional and supports both 2.xD and 3D connectivity. UCle-3D is designed for lower frequencies and shorter distances, simplifying the circuit design and reducing power consumption. The PHY architecture for UCle-3D is based on a forwarded-clock structure with simple setup and hold specifications. The NoC directly interfaces with the UCle-3D circuits, eliminating the need for a D2D adaptor. The article also presents an analysis of the efficiency of the UCle-3D approach, including power and performance comparisons with monolithic solutions. The results show that UCle-3D offers superior performance with lower latency, higher bisection bandwidth, and lower bandwidth demand compared to planar implementations. The authors conclude that UCle-3D is a power-performance-efficient and cost-effective method for constructing System-in-Package (SiP) architectures using emerging advanced 3D packaging technologies with shrinking bump pitches.The article discusses the development and performance of Universal Chiplet Interconnect Express (UCle) 1.0, an open industry standard interconnect for chiplet ecosystems. UCle 1.0 supports interoperability using standard and advanced packaging technologies with planar interconnects. The authors examine how UCle can evolve as bump interconnect pitches reduce with advances in packaging technologies for three-dimensional (3D) integration of chiplets. They report a die-to-die solution for package bump pitches down to 1 μm, providing circuit architecture details and performance results. The analysis suggests that reducing the frequency as the bump pitch decreases can achieve the most power-efficient performance. The proposed architectural approach offers power, performance, and reliability characteristics comparable to or exceeding those of monolithic system-on-chip designs as the bump pitch approaches 1 μm. UCle 1.0 defines two types of packaging: standard (UCle-S) and advanced (UCle-A). The standard package is cost-effective, while the advanced package is power-efficient. UCle supports different data rates, widths, bump pitches, and channel reach to ensure interoperability. The physical layer (PHY) handles electrical signaling, clocking, link training, and circuit architecture. The basic unit is a module comprising multiple data lanes, validation and tracking lanes, and a differential forwarded-clock per direction. The authors propose a next-generation UCle, referred to as UCle-3D, which is unidirectional and supports both 2.xD and 3D connectivity. UCle-3D is designed for lower frequencies and shorter distances, simplifying the circuit design and reducing power consumption. The PHY architecture for UCle-3D is based on a forwarded-clock structure with simple setup and hold specifications. The NoC directly interfaces with the UCle-3D circuits, eliminating the need for a D2D adaptor. The article also presents an analysis of the efficiency of the UCle-3D approach, including power and performance comparisons with monolithic solutions. The results show that UCle-3D offers superior performance with lower latency, higher bisection bandwidth, and lower bandwidth demand compared to planar implementations. The authors conclude that UCle-3D is a power-performance-efficient and cost-effective method for constructing System-in-Package (SiP) architectures using emerging advanced 3D packaging technologies with shrinking bump pitches.