This paper presents a pseudo-CMOS architecture for sub-picowatt logic computing using self-biased molybdenum disulfide (MoS₂) transistors. The key innovation is the introduction of a gapped channel in the MoS₂ transistor, which forms a tunable barrier and overcomes the limitations of 2D materials in polarity control. This design allows for a reverse saturation current below 1 pA with high reliability and endurance. The authors fabricate homojunction-loaded inverters with rail-to-rail operation, a switching threshold voltage of around 0.5 V, a static power of a few picowatts, a dynamic delay time of about 200 μs, a noise margin over 90%, and a peak voltage gain of 241. They also demonstrate the implementation of fundamental gate circuits, including NAND, NOR, AND, OR, and XOR gates, using this pseudo-CMOS configuration. The results show that the pseudo-CMOS inverter outperforms conventional CMOS and pseudo-NMOS inverters in terms of static power, noise margin, and voltage gain, making it a promising approach for future integrated circuits that balance power consumption and operating speed.This paper presents a pseudo-CMOS architecture for sub-picowatt logic computing using self-biased molybdenum disulfide (MoS₂) transistors. The key innovation is the introduction of a gapped channel in the MoS₂ transistor, which forms a tunable barrier and overcomes the limitations of 2D materials in polarity control. This design allows for a reverse saturation current below 1 pA with high reliability and endurance. The authors fabricate homojunction-loaded inverters with rail-to-rail operation, a switching threshold voltage of around 0.5 V, a static power of a few picowatts, a dynamic delay time of about 200 μs, a noise margin over 90%, and a peak voltage gain of 241. They also demonstrate the implementation of fundamental gate circuits, including NAND, NOR, AND, OR, and XOR gates, using this pseudo-CMOS configuration. The results show that the pseudo-CMOS inverter outperforms conventional CMOS and pseudo-NMOS inverters in terms of static power, noise margin, and voltage gain, making it a promising approach for future integrated circuits that balance power consumption and operating speed.