This paper presents a novel pseudo-CMOS logic architecture for sub-picowatt computing using self-biased molybdenum disulfide (MoS₂) transistors. The key innovation is the use of a homojunction-loaded inverter, which utilizes a self-biased MoS₂ transistor as the load and an n-FET as the driver. The MoS₂ transistor features a gapped channel that forms a tunable barrier, enabling the inverter to operate with minimal static power and high reliability. The inverter achieves rail-to-rail operation at a switching threshold voltage of around 0.5 V, with a static power of a few picowatts, a dynamic delay time of around 200 μs, a noise margin over 90%, and a peak voltage gain of 241. The architecture effectively circumvents the polarity control limitations of 2D materials, resulting in significantly reduced static power compared to conventional pseudo-NMOS and CMOS configurations. The inverter is also capable of implementing various Boolean logic functions, including XOR, AND, NAND, NOR, and OR gates, demonstrating its versatility for low-power logic computing. The study further shows that the pseudo-CMOS inverter can achieve an ultrahigh rectification ratio of ~10⁹ with an ultralow reverse saturation current below 1 pA, making it suitable for high-performance, low-power circuits. The research highlights the potential of MoS₂-based transistors in next-generation computing technologies, offering a promising path for developing energy-efficient integrated circuits.This paper presents a novel pseudo-CMOS logic architecture for sub-picowatt computing using self-biased molybdenum disulfide (MoS₂) transistors. The key innovation is the use of a homojunction-loaded inverter, which utilizes a self-biased MoS₂ transistor as the load and an n-FET as the driver. The MoS₂ transistor features a gapped channel that forms a tunable barrier, enabling the inverter to operate with minimal static power and high reliability. The inverter achieves rail-to-rail operation at a switching threshold voltage of around 0.5 V, with a static power of a few picowatts, a dynamic delay time of around 200 μs, a noise margin over 90%, and a peak voltage gain of 241. The architecture effectively circumvents the polarity control limitations of 2D materials, resulting in significantly reduced static power compared to conventional pseudo-NMOS and CMOS configurations. The inverter is also capable of implementing various Boolean logic functions, including XOR, AND, NAND, NOR, and OR gates, demonstrating its versatility for low-power logic computing. The study further shows that the pseudo-CMOS inverter can achieve an ultrahigh rectification ratio of ~10⁹ with an ultralow reverse saturation current below 1 pA, making it suitable for high-performance, low-power circuits. The research highlights the potential of MoS₂-based transistors in next-generation computing technologies, offering a promising path for developing energy-efficient integrated circuits.