LDPC-cat codes for low-overhead quantum computing in 2D Diego Ruiz, Jérémie Guillaume, Anthony Leverrier, Mazyar Mirrahimi, and Christophe Vuillot Quantum low-density parity-check (qLDPC) codes are promising for reducing the overhead of fault-tolerant quantum computing (FTQC). However, existing implementations require advanced technologies like long-range qubit connectivity or multi-layered chip layouts. An alternative approach is to use bosonic cat qubits, where bit-flip errors are exponentially suppressed. This work combines both approaches, proposing an architecture based on cat qubits concatenated in classical LDPC codes to correct phase-flips. The hardware implementation can use short-range qubit interactions and low-weight stabilizers, making it compatible with current superconducting circuit technologies. A second layer of cat qubits enables fault-tolerant universal logical gates while maintaining local connectivity. Numerical optimization of classical codes finds those with the best encoding rates for algorithmically relevant distances. Some of the best codes benefit from a cellular automaton structure, allowing high encoding rates and distances. Under circuit-level noise with a physical phase-flip error probability of ~0.1%, the [165+8ℓ,34+2ℓ,22] code family can encode 100 logical qubits with a total logical error probability of ~10⁻⁸. The paper discusses the theoretical and experimental research on quantum error correction and fault-tolerant quantum computing. It highlights the surface code's high threshold and its limitations in terms of encoding rate and overhead. The paper also explores the use of cat qubits, which have exponentially suppressed bit-flip errors. The main result is the reduction of the cat qubit architecture's footprint by replacing the repetition code with classical LDPC codes with improved encoding rates, while retaining the capability of executing a universal set of fault-tolerant logical gates. The paper presents a comparison of the footprint and key technological assumptions of the architecture with other alternatives. It also discusses the implementation of a universal set of fault-tolerant logical gates using ancillary logical qubits encoded in repetition codes. The paper concludes with a discussion of the experimental implementation of the architecture in a superconducting circuits platform.LDPC-cat codes for low-overhead quantum computing in 2D Diego Ruiz, Jérémie Guillaume, Anthony Leverrier, Mazyar Mirrahimi, and Christophe Vuillot Quantum low-density parity-check (qLDPC) codes are promising for reducing the overhead of fault-tolerant quantum computing (FTQC). However, existing implementations require advanced technologies like long-range qubit connectivity or multi-layered chip layouts. An alternative approach is to use bosonic cat qubits, where bit-flip errors are exponentially suppressed. This work combines both approaches, proposing an architecture based on cat qubits concatenated in classical LDPC codes to correct phase-flips. The hardware implementation can use short-range qubit interactions and low-weight stabilizers, making it compatible with current superconducting circuit technologies. A second layer of cat qubits enables fault-tolerant universal logical gates while maintaining local connectivity. Numerical optimization of classical codes finds those with the best encoding rates for algorithmically relevant distances. Some of the best codes benefit from a cellular automaton structure, allowing high encoding rates and distances. Under circuit-level noise with a physical phase-flip error probability of ~0.1%, the [165+8ℓ,34+2ℓ,22] code family can encode 100 logical qubits with a total logical error probability of ~10⁻⁸. The paper discusses the theoretical and experimental research on quantum error correction and fault-tolerant quantum computing. It highlights the surface code's high threshold and its limitations in terms of encoding rate and overhead. The paper also explores the use of cat qubits, which have exponentially suppressed bit-flip errors. The main result is the reduction of the cat qubit architecture's footprint by replacing the repetition code with classical LDPC codes with improved encoding rates, while retaining the capability of executing a universal set of fault-tolerant logical gates. The paper presents a comparison of the footprint and key technological assumptions of the architecture with other alternatives. It also discusses the implementation of a universal set of fault-tolerant logical gates using ancillary logical qubits encoded in repetition codes. The paper concludes with a discussion of the experimental implementation of the architecture in a superconducting circuits platform.