The paper introduces memory access scheduling, a technique that optimizes the performance of memory systems by reordering memory references to exploit locality within the 3-D structure of banks, rows, and columns in contemporary DRAM chips. The authors demonstrate that this technique can significantly improve memory bandwidth, with conservative reordering increasing bandwidth by 40% and aggressive reordering improving it by up to 93% for media processing applications. The paper discusses the characteristics of modern DRAM architecture, the design of memory access schedulers, and experimental results showing the effectiveness of different scheduling algorithms. The authors also explore the impact of bank buffer size and load-over-store policies on memory bandwidth. The paper concludes by highlighting the importance of memory access scheduling in maximizing memory bandwidth, especially in media processing systems where streaming data types do not cache well.The paper introduces memory access scheduling, a technique that optimizes the performance of memory systems by reordering memory references to exploit locality within the 3-D structure of banks, rows, and columns in contemporary DRAM chips. The authors demonstrate that this technique can significantly improve memory bandwidth, with conservative reordering increasing bandwidth by 40% and aggressive reordering improving it by up to 93% for media processing applications. The paper discusses the characteristics of modern DRAM architecture, the design of memory access schedulers, and experimental results showing the effectiveness of different scheduling algorithms. The authors also explore the impact of bank buffer size and load-over-store policies on memory bandwidth. The paper concludes by highlighting the importance of memory access scheduling in maximizing memory bandwidth, especially in media processing systems where streaming data types do not cache well.