This paper presents a comprehensive review of recent advancements and research directions aimed at addressing the challenges of training and deploying Large Language Models (LLMs), with a focus on algorithm-level acceleration, hardware co-design, and LLM-to-accelerator compilation. The paper discusses various techniques for optimizing LLM inference speed and resource utilization, including efficient parameter utilization, KV cache optimization, and parallel decoding. It also explores LLM-hardware co-design strategies to improve system efficiency by tailoring hardware architectures to LLM requirements. Additionally, the paper delves into LLM-to-accelerator compilation approaches, which involve customizing hardware accelerators for efficient LLM deployment. As a case study, the paper examines LLM-aided design methodologies for High-Level Synthesis (HLS) functional verification by creating a new dataset containing a large number of buggy and bug-free codes, which can be essential for training LLMs to specialize on HLS verification and debugging. The paper also outlines future research directions to drive further advancements in LLM efficiency and effectiveness. The paper concludes with a discussion of the potential of LLMs in various applications, including EDA, and highlights the importance of optimizing LLMs for efficient deployment across diverse applications.This paper presents a comprehensive review of recent advancements and research directions aimed at addressing the challenges of training and deploying Large Language Models (LLMs), with a focus on algorithm-level acceleration, hardware co-design, and LLM-to-accelerator compilation. The paper discusses various techniques for optimizing LLM inference speed and resource utilization, including efficient parameter utilization, KV cache optimization, and parallel decoding. It also explores LLM-hardware co-design strategies to improve system efficiency by tailoring hardware architectures to LLM requirements. Additionally, the paper delves into LLM-to-accelerator compilation approaches, which involve customizing hardware accelerators for efficient LLM deployment. As a case study, the paper examines LLM-aided design methodologies for High-Level Synthesis (HLS) functional verification by creating a new dataset containing a large number of buggy and bug-free codes, which can be essential for training LLMs to specialize on HLS verification and debugging. The paper also outlines future research directions to drive further advancements in LLM efficiency and effectiveness. The paper concludes with a discussion of the potential of LLMs in various applications, including EDA, and highlights the importance of optimizing LLMs for efficient deployment across diverse applications.