Photonic networks-on-chip (NoCs) offer a promising solution to reduce power dissipation in chip multiprocessors (CMPs). By leveraging the low loss and high bandwidth of optical waveguides, photonic NoCs can provide significantly lower power consumption and higher bandwidth compared to traditional electronic NoCs. This paper presents a hybrid microarchitecture combining a broadband photonic circuit-switched network with an electronic packet-switched control network. This design allows for efficient communication of large messages through the photonic network and short messages through the electronic network. The paper addresses critical design issues including topology, routing algorithms, deadlock avoidance, and path-setup/teardown procedures. Experimental results from the POINTS simulator confirm the potential performance improvements of photonic NoCs in future CMPs. The results show that photonic NoCs can reduce intrachip communication power consumption by nearly two orders of magnitude when high-bandwidth communications are required among a large number of cores. The paper also discusses the challenges of implementing photonic NoCs, including the need for advanced photonic integration with commercial CMOS processes and the design of a hybrid NoC microarchitecture that combines photonic and electronic technologies. The proposed design allows for efficient communication between processing cores and off-chip memories and devices, and is expected to be implemented using 3D integration technology. The paper concludes that photonic NoCs offer significant advantages in terms of power efficiency and performance for future CMPs.Photonic networks-on-chip (NoCs) offer a promising solution to reduce power dissipation in chip multiprocessors (CMPs). By leveraging the low loss and high bandwidth of optical waveguides, photonic NoCs can provide significantly lower power consumption and higher bandwidth compared to traditional electronic NoCs. This paper presents a hybrid microarchitecture combining a broadband photonic circuit-switched network with an electronic packet-switched control network. This design allows for efficient communication of large messages through the photonic network and short messages through the electronic network. The paper addresses critical design issues including topology, routing algorithms, deadlock avoidance, and path-setup/teardown procedures. Experimental results from the POINTS simulator confirm the potential performance improvements of photonic NoCs in future CMPs. The results show that photonic NoCs can reduce intrachip communication power consumption by nearly two orders of magnitude when high-bandwidth communications are required among a large number of cores. The paper also discusses the challenges of implementing photonic NoCs, including the need for advanced photonic integration with commercial CMOS processes and the design of a hybrid NoC microarchitecture that combines photonic and electronic technologies. The proposed design allows for efficient communication between processing cores and off-chip memories and devices, and is expected to be implemented using 3D integration technology. The paper concludes that photonic NoCs offer significant advantages in terms of power efficiency and performance for future CMPs.