Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

SEPTEMBER 2008 | Assaf Shacham, Member, IEEE, Keren Bergman, Senior Member, IEEE, and Luca P. Carloni, Member, IEEE
The paper discusses the design and performance of photonic networks-on-chip (NoC) for next-generation chip multiprocessors (CMPs), aiming to reduce power dissipation and improve communication efficiency. The authors propose a hybrid microarchitecture that combines a broadband photonic circuit-switched network with an electronic packet-switched control network. This design leverages the low-loss properties of optical waveguides and bit-rate transparency, allowing for higher bandwidth and lower latencies with significantly reduced power consumption compared to electronic NoCs. The paper addresses critical design issues such as topology, routing algorithms, deadlock avoidance, and path-setup/teardown procedures. Experimental results from the POINTS simulator and a comparative power analysis confirm the benefits of photonic NoCs in terms of power efficiency and performance for future CMPs. The proposed hybrid NoC microarchitecture is designed to handle both large and small messages efficiently, with large messages transmitted through the photonic network and small messages handled electronically. The paper also explores methods to optimize message size and reduce contention, ensuring optimal performance and power efficiency.The paper discusses the design and performance of photonic networks-on-chip (NoC) for next-generation chip multiprocessors (CMPs), aiming to reduce power dissipation and improve communication efficiency. The authors propose a hybrid microarchitecture that combines a broadband photonic circuit-switched network with an electronic packet-switched control network. This design leverages the low-loss properties of optical waveguides and bit-rate transparency, allowing for higher bandwidth and lower latencies with significantly reduced power consumption compared to electronic NoCs. The paper addresses critical design issues such as topology, routing algorithms, deadlock avoidance, and path-setup/teardown procedures. Experimental results from the POINTS simulator and a comparative power analysis confirm the benefits of photonic NoCs in terms of power efficiency and performance for future CMPs. The proposed hybrid NoC microarchitecture is designed to handle both large and small messages efficiently, with large messages transmitted through the photonic network and small messages handled electronically. The paper also explores methods to optimize message size and reduce contention, ensuring optimal performance and power efficiency.
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