The invention discloses a combined Chien search and error position circuit for Reed-Solomon decoding. The circuit operates in response to a zero signal issued by a root detection block, which iteratively evaluates an error locator polynomial over the Galois field used in the coding. The circuit includes a zeroes register, a position register, an index counter, an exponentiation circuit, and a root counter. The index counter maintains a count over the Galois field, corresponding to the Galois field element under evaluation. The exponentiation circuit performs Galois field exponentiation and applies the result to the inputs of the zeroes register stages. The root counter maintains a count of the number of roots identified by the root detection block, which is used to sequentially select the register stages into which the zeroes and position values are stored. The invention provides an efficient implementation of Chien search and error position locating circuitry for use in Reed-Solomon decoding, without the need for look-up tables and can be realized in a programmable logic device such as a digital signal processor or microprocessor.The invention discloses a combined Chien search and error position circuit for Reed-Solomon decoding. The circuit operates in response to a zero signal issued by a root detection block, which iteratively evaluates an error locator polynomial over the Galois field used in the coding. The circuit includes a zeroes register, a position register, an index counter, an exponentiation circuit, and a root counter. The index counter maintains a count over the Galois field, corresponding to the Galois field element under evaluation. The exponentiation circuit performs Galois field exponentiation and applies the result to the inputs of the zeroes register stages. The root counter maintains a count of the number of roots identified by the root detection block, which is used to sequentially select the register stages into which the zeroes and position values are stored. The invention provides an efficient implementation of Chien search and error position locating circuitry for use in Reed-Solomon decoding, without the need for look-up tables and can be realized in a programmable logic device such as a digital signal processor or microprocessor.