A combined Chien search and error position circuit for Reed-Solomon decoding is disclosed. The circuit operates in response to a zero signal issued by a root detection block that iteratively evaluates an error locator polynomial over the Galois field used in the coding. A zeroes register and a position register are provided, each with multiple stages. An index counter maintains a count over the Galois field, corresponding to the Galois field element under evaluation in the root detection block. An exponentiation circuit performs a Galois field exponentiation of the count and applies the result to the inputs of each of the zeroes register stages. The count is subtracted from the maximum Galois field index and, for all but the zeroth iteration, the difference is applied to the inputs of each of the position register stages. A root counter maintains a count of the number of roots identified by the root detection block, which is used to sequentially select the register stages into which the zeroes and position values are stored. The invention provides an efficient implementation of Chien search and error position locating circuitry for use in Reed-Solomon decoding. It also provides such circuitry that may be realized without look-up tables for the error position circuitry and may be implemented into a programmable logic device such as a digital signal processor or microprocessor. The combined Chien search and error position function is implemented as a functional unit within a programmable logic device, such as a digital signal processor or general-purpose microprocessor. The error position results are generated by subtracting, from the maximum finite field value minus one, a count corresponding to the power representation of a detected root of an error locator polynomial. The value of this subtraction exactly equals the byte position within the frame of an erred byte, and thus may be used to indicate the position of errors in the input bitstream. The error position polynomial may be generated without performing the logarithm of the reciprocal of the members of the Chien search zeroes polynomial. The invention significantly reduces the chip area, hardware complexity, and computational cost by simplifying the generation of the error position polynomial coefficients. The invention is particularly beneficial in applications such as digital subscriber line (DSL) modems, where Reed-Solomon decoding is used for error correction.A combined Chien search and error position circuit for Reed-Solomon decoding is disclosed. The circuit operates in response to a zero signal issued by a root detection block that iteratively evaluates an error locator polynomial over the Galois field used in the coding. A zeroes register and a position register are provided, each with multiple stages. An index counter maintains a count over the Galois field, corresponding to the Galois field element under evaluation in the root detection block. An exponentiation circuit performs a Galois field exponentiation of the count and applies the result to the inputs of each of the zeroes register stages. The count is subtracted from the maximum Galois field index and, for all but the zeroth iteration, the difference is applied to the inputs of each of the position register stages. A root counter maintains a count of the number of roots identified by the root detection block, which is used to sequentially select the register stages into which the zeroes and position values are stored. The invention provides an efficient implementation of Chien search and error position locating circuitry for use in Reed-Solomon decoding. It also provides such circuitry that may be realized without look-up tables for the error position circuitry and may be implemented into a programmable logic device such as a digital signal processor or microprocessor. The combined Chien search and error position function is implemented as a functional unit within a programmable logic device, such as a digital signal processor or general-purpose microprocessor. The error position results are generated by subtracting, from the maximum finite field value minus one, a count corresponding to the power representation of a detected root of an error locator polynomial. The value of this subtraction exactly equals the byte position within the frame of an erred byte, and thus may be used to indicate the position of errors in the input bitstream. The error position polynomial may be generated without performing the logarithm of the reciprocal of the members of the Chien search zeroes polynomial. The invention significantly reduces the chip area, hardware complexity, and computational cost by simplifying the generation of the error position polynomial coefficients. The invention is particularly beneficial in applications such as digital subscriber line (DSL) modems, where Reed-Solomon decoding is used for error correction.