This paper presents theoretical foundations for securing hardware against side channel attacks, which are a significant threat to cryptographic implementations. The authors propose efficient techniques for building private circuits that resist such attacks. They introduce a formal threat model and prove the security of their constructions, addressing the limitations of previous hardware countermeasures that are tailored to specific side channels. The paper also explores the complexity of private circuits and provides a systematic study of their security properties. The authors define a model where an adversary can observe up to t internal wires of a circuit during one clock cycle. They show how to transform any circuit into a larger circuit that remains secure even if the adversary observes up to t internal bits. This transformation increases the circuit size by a factor of O(t²), but for specific cryptosystems like pseudorandom generators (PRGs), the size can be reduced to O(nt). The constructions are provably secure and apply to any cryptosystem, not just AES encryption. The paper also discusses statistically private transformers that improve the efficiency of previous constructions when the privacy threshold t is large. These transformers use sorting networks and other techniques to achieve average-case security, reducing the number of random bits required. The constructions are shown to be secure against both stateless and stateful circuits, with the latter being more practical for real-world applications. The authors emphasize the importance of theoretical foundations in cryptography, arguing that ad-hoc countermeasures are insufficient. They provide a formal model of the adversary, define security against probing attacks, and prove the security of their constructions. The results show that the cost of security is manageable, as many cryptosystems can be implemented efficiently in hardware, and the use of big-O notation does not hide large constants. The paper concludes with a detailed discussion of the relationship between their problem and secure multi-party computation (MPC), highlighting the practical implications of their findings.This paper presents theoretical foundations for securing hardware against side channel attacks, which are a significant threat to cryptographic implementations. The authors propose efficient techniques for building private circuits that resist such attacks. They introduce a formal threat model and prove the security of their constructions, addressing the limitations of previous hardware countermeasures that are tailored to specific side channels. The paper also explores the complexity of private circuits and provides a systematic study of their security properties. The authors define a model where an adversary can observe up to t internal wires of a circuit during one clock cycle. They show how to transform any circuit into a larger circuit that remains secure even if the adversary observes up to t internal bits. This transformation increases the circuit size by a factor of O(t²), but for specific cryptosystems like pseudorandom generators (PRGs), the size can be reduced to O(nt). The constructions are provably secure and apply to any cryptosystem, not just AES encryption. The paper also discusses statistically private transformers that improve the efficiency of previous constructions when the privacy threshold t is large. These transformers use sorting networks and other techniques to achieve average-case security, reducing the number of random bits required. The constructions are shown to be secure against both stateless and stateful circuits, with the latter being more practical for real-world applications. The authors emphasize the importance of theoretical foundations in cryptography, arguing that ad-hoc countermeasures are insufficient. They provide a formal model of the adversary, define security against probing attacks, and prove the security of their constructions. The results show that the cost of security is manageable, as many cryptosystems can be implemented efficiently in hardware, and the use of big-O notation does not hide large constants. The paper concludes with a detailed discussion of the relationship between their problem and secure multi-party computation (MPC), highlighting the practical implications of their findings.