This paper presents a novel approach using reinforcement learning (RL) to automatically discover compact and hardware-adapted fault-tolerant quantum circuits for logical state preparation. The goal is to design circuits that can prepare logical states of quantum error-correcting (QEC) codes while minimizing the number of gates and ancillary qubits, and ensuring fault tolerance. The method is tested on several QEC codes, including the 5-qubit perfect code, the 7-qubit Steane code, the 9-qubit Shor code, and the 15-qubit Reed-Muller code. The RL agent is trained to find optimal strategies for preparing logical states under hardware constraints, such as qubit connectivity and gate set. The results show that the RL method outperforms existing methods in terms of circuit size and efficiency. The approach is also extended to synthesis of verification circuits that use flag qubits to flag harmful errors, ensuring fault tolerance. The RL method is shown to be effective in handling different qubit connectivities and gate sets, and can be accelerated through transfer learning. The work demonstrates the potential of RL for discovering fault-tolerant quantum circuits for a variety of tasks beyond state preparation, including magic state preparation, logical gate synthesis, and syndrome measurement.This paper presents a novel approach using reinforcement learning (RL) to automatically discover compact and hardware-adapted fault-tolerant quantum circuits for logical state preparation. The goal is to design circuits that can prepare logical states of quantum error-correcting (QEC) codes while minimizing the number of gates and ancillary qubits, and ensuring fault tolerance. The method is tested on several QEC codes, including the 5-qubit perfect code, the 7-qubit Steane code, the 9-qubit Shor code, and the 15-qubit Reed-Muller code. The RL agent is trained to find optimal strategies for preparing logical states under hardware constraints, such as qubit connectivity and gate set. The results show that the RL method outperforms existing methods in terms of circuit size and efficiency. The approach is also extended to synthesis of verification circuits that use flag qubits to flag harmful errors, ensuring fault tolerance. The RL method is shown to be effective in handling different qubit connectivities and gate sets, and can be accelerated through transfer learning. The work demonstrates the potential of RL for discovering fault-tolerant quantum circuits for a variety of tasks beyond state preparation, including magic state preparation, logical gate synthesis, and syndrome measurement.