The paper discusses the possibility of achieving accurate quantum computing with error probabilities above 3% per gate, which is significantly higher than previously thought possible. The authors present a fault-tolerant architecture called the "C4/C6 architecture" that can handle such high error rates, although the resources required are excessive. The C4/C6 architecture uses simple error-detecting codes and error-correcting teleportation to minimize the number of gates contributing to errors. The authors also explore the use of postselected computing, which can achieve higher thresholds than standard quantum computing. They demonstrate that the C4/C6 architecture can enable scalable quantum computing at error probabilities as high as 1% per gate, provided that resources are optimized. The paper includes detailed analyses of the error behavior, resource requirements, and comparisons with other fault-tolerant architectures.The paper discusses the possibility of achieving accurate quantum computing with error probabilities above 3% per gate, which is significantly higher than previously thought possible. The authors present a fault-tolerant architecture called the "C4/C6 architecture" that can handle such high error rates, although the resources required are excessive. The C4/C6 architecture uses simple error-detecting codes and error-correcting teleportation to minimize the number of gates contributing to errors. The authors also explore the use of postselected computing, which can achieve higher thresholds than standard quantum computing. They demonstrate that the C4/C6 architecture can enable scalable quantum computing at error probabilities as high as 1% per gate, provided that resources are optimized. The paper includes detailed analyses of the error behavior, resource requirements, and comparisons with other fault-tolerant architectures.