Razor is a low-power pipeline based on circuit-level timing speculation, designed to dynamically adjust supply voltage based on error rates during circuit operation. This approach eliminates the need for voltage margins and exploits the data dependence of circuit delay. The key idea of Razor is to tune the supply voltage by monitoring the error rate during operation, thereby ensuring correct operation while minimizing power consumption. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of a timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. Razor energy overheads during normal operation are limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%). The Razor approach automatically exploits the data-dependence of circuit delay by tuning the supply voltage to obtain a small, but non-zero error rate. It was found that if the error rate is maintained sufficiently low, the power overhead from error correction is minimal, while substantial power savings are obtained due to operating the circuit at a lower supply voltage. The proposed Razor technique was implemented in a prototype 64-bit Alpha processor design. This prototype implementation was used to obtain a realistic prediction of the power overhead for in-situ error correction and detection. We also studied the error-rate trends for datapath components using both circuit-level simulation as well as silicon measurements of a full-custom multiplier block. Architectural simulations were then performed to analyze the overall throughput and power characteristics of Razor based DVS for different benchmark test programs. We demonstrate that on average, Razor reduced simulated power consumption by more than 40%, compared to traditional design-time DVS and delay-chain based approaches. The remainder of this paper is organized as follows. In Section 2, we present the implementation of Razor, providing a detailed description of both the proposed circuit and architectural techniques. In Section 3, we discuss the simulation framework for Razor-based DVS and present error rate studies and our simulation results. In Section 4, we present a detailed survey of prior work in DVS. Finally, in Section 5, we draw our conclusions.Razor is a low-power pipeline based on circuit-level timing speculation, designed to dynamically adjust supply voltage based on error rates during circuit operation. This approach eliminates the need for voltage margins and exploits the data dependence of circuit delay. The key idea of Razor is to tune the supply voltage by monitoring the error rate during operation, thereby ensuring correct operation while minimizing power consumption. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of a timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. Razor energy overheads during normal operation are limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%). The Razor approach automatically exploits the data-dependence of circuit delay by tuning the supply voltage to obtain a small, but non-zero error rate. It was found that if the error rate is maintained sufficiently low, the power overhead from error correction is minimal, while substantial power savings are obtained due to operating the circuit at a lower supply voltage. The proposed Razor technique was implemented in a prototype 64-bit Alpha processor design. This prototype implementation was used to obtain a realistic prediction of the power overhead for in-situ error correction and detection. We also studied the error-rate trends for datapath components using both circuit-level simulation as well as silicon measurements of a full-custom multiplier block. Architectural simulations were then performed to analyze the overall throughput and power characteristics of Razor based DVS for different benchmark test programs. We demonstrate that on average, Razor reduced simulated power consumption by more than 40%, compared to traditional design-time DVS and delay-chain based approaches. The remainder of this paper is organized as follows. In Section 2, we present the implementation of Razor, providing a detailed description of both the proposed circuit and architectural techniques. In Section 3, we discuss the simulation framework for Razor-based DVS and present error rate studies and our simulation results. In Section 4, we present a detailed survey of prior work in DVS. Finally, in Section 5, we draw our conclusions.