The paper introduces Razor, a novel approach to dynamic voltage scaling (DVS) that leverages circuit-level timing speculation to dynamically adjust the supply voltage based on the error rate during operation. The key idea is to tune the supply voltage by monitoring and correcting circuit timing errors, eliminating the need for conservative voltage margins. A Razor flip-flop is designed to double-sample pipeline stage values with a fast clock and a delayed clock, and a metastability-tolerant comparator validates latch values. In the event of a timing error, a modified pipeline mis-speculation recovery mechanism restores the correct program state. The prototype Razor pipeline was implemented in 0.18 μm technology, showing an energy overhead of 3.1% during normal operation. Simulations of a full-custom multiplier and a SPICE-level Kogge-Stone adder model demonstrate significant energy savings (up to 64.2%) with minimal performance impact due to error recovery. The paper also discusses the implementation details, error detection and correction mechanisms, and experimental evaluation, including power analysis and error rate studies.The paper introduces Razor, a novel approach to dynamic voltage scaling (DVS) that leverages circuit-level timing speculation to dynamically adjust the supply voltage based on the error rate during operation. The key idea is to tune the supply voltage by monitoring and correcting circuit timing errors, eliminating the need for conservative voltage margins. A Razor flip-flop is designed to double-sample pipeline stage values with a fast clock and a delayed clock, and a metastability-tolerant comparator validates latch values. In the event of a timing error, a modified pipeline mis-speculation recovery mechanism restores the correct program state. The prototype Razor pipeline was implemented in 0.18 μm technology, showing an energy overhead of 3.1% during normal operation. Simulations of a full-custom multiplier and a SPICE-level Kogge-Stone adder model demonstrate significant energy savings (up to 64.2%) with minimal performance impact due to error recovery. The paper also discusses the implementation details, error detection and correction mechanisms, and experimental evaluation, including power analysis and error rate studies.