SIS is an interactive tool for synthesizing and optimizing sequential circuits. It takes as input a state transition table, a signal transition graph, or a logic-level description of a sequential circuit and produces an optimized net-list in the target technology while preserving the sequential input-output behavior. SIS integrates many different programs and algorithms, allowing users to choose among various techniques at each stage of the process. It is built on top of MISII and includes all combinational optimization techniques from MISII as well as many enhancements. SIS serves as both a framework for testing and comparing various algorithms and as a tool for automatic synthesis and optimization of sequential circuits. SIS supports a design methodology that allows designers to search a larger solution space than previously possible. It is used for sequential circuit synthesis and optimization, and is built on top of MISII, replacing it in the Octtools, a Berkeley synthesis tool set based on the Oct database. While MISII operated on only combinational circuits, SIS handles both combinational and sequential circuits. In the Octtools environment, a behavioral description of combinational logic can be given in a subset of the BDS language. The program bdsyn is used to translate this description into a set of logic equations, and then bdnet is used to connect combinational logic and registers and create an Oct description file. Alternatively, the starting point can be a state transition table, and SIS is used to invoke state assignment programs to create the initial logic implementation, or a signal transition graph, and SIS is used to create a hazard-free logic implementation. SIS is then used for optimization and technology mapping; placement and routing tools in the Octtools produce a symbolic layout for the circuit. The SIS environment is similar to MISII: optimization is done for area, performance, and testability. System-level timing constraints can be specified for the I/O pins. External "don't care" conditions can be supplied and used in the optimization. Synthesis proceeds in several phases: state minimization and state assignment, global area minimization and performance optimization, local optimization, and technology mapping. SIS is interactive, but as in MISII, scripts are provided to automate the process and guide the optimization steps. SIS contains many new operations and algorithms, and it is the combination of these within a uniform framework that allows the designer to explore a large design space. Some of these are enhancements to the combinational techniques previously employed in MISII. These include improvements to performance optimization, storage and use of external don't cares, improved node minimization, and faster divisor extraction. In addition, new sequential techniques are included: an interface to state minimization and state assignment programs, retiming, sequential circuit optimization algorithms, finite-state machine verification, technology mapping for sequential circuits, and synthesis of asynchronous designs. SIS contains MISII and all the combinational optimization techniques therein. This includes the global area minimization strategy, combinational speed-up techniques based on local restructuring,SIS is an interactive tool for synthesizing and optimizing sequential circuits. It takes as input a state transition table, a signal transition graph, or a logic-level description of a sequential circuit and produces an optimized net-list in the target technology while preserving the sequential input-output behavior. SIS integrates many different programs and algorithms, allowing users to choose among various techniques at each stage of the process. It is built on top of MISII and includes all combinational optimization techniques from MISII as well as many enhancements. SIS serves as both a framework for testing and comparing various algorithms and as a tool for automatic synthesis and optimization of sequential circuits. SIS supports a design methodology that allows designers to search a larger solution space than previously possible. It is used for sequential circuit synthesis and optimization, and is built on top of MISII, replacing it in the Octtools, a Berkeley synthesis tool set based on the Oct database. While MISII operated on only combinational circuits, SIS handles both combinational and sequential circuits. In the Octtools environment, a behavioral description of combinational logic can be given in a subset of the BDS language. The program bdsyn is used to translate this description into a set of logic equations, and then bdnet is used to connect combinational logic and registers and create an Oct description file. Alternatively, the starting point can be a state transition table, and SIS is used to invoke state assignment programs to create the initial logic implementation, or a signal transition graph, and SIS is used to create a hazard-free logic implementation. SIS is then used for optimization and technology mapping; placement and routing tools in the Octtools produce a symbolic layout for the circuit. The SIS environment is similar to MISII: optimization is done for area, performance, and testability. System-level timing constraints can be specified for the I/O pins. External "don't care" conditions can be supplied and used in the optimization. Synthesis proceeds in several phases: state minimization and state assignment, global area minimization and performance optimization, local optimization, and technology mapping. SIS is interactive, but as in MISII, scripts are provided to automate the process and guide the optimization steps. SIS contains many new operations and algorithms, and it is the combination of these within a uniform framework that allows the designer to explore a large design space. Some of these are enhancements to the combinational techniques previously employed in MISII. These include improvements to performance optimization, storage and use of external don't cares, improved node minimization, and faster divisor extraction. In addition, new sequential techniques are included: an interface to state minimization and state assignment programs, retiming, sequential circuit optimization algorithms, finite-state machine verification, technology mapping for sequential circuits, and synthesis of asynchronous designs. SIS contains MISII and all the combinational optimization techniques therein. This includes the global area minimization strategy, combinational speed-up techniques based on local restructuring,