SIS is an interactive tool for the synthesis and optimization of sequential circuits, designed to explore a larger solution space compared to traditional methods. It supports various input specifications, including state transition tables, signal transition graphs, and logic-level descriptions. SIS integrates multiple algorithms and techniques, allowing users to choose among different methods at each stage of the process. The system is built on top of MISII and includes enhancements for combinational optimization, such as improved performance optimization, storage and use of external don't cares, and faster divisor extraction. New sequential techniques include state minimization, state assignment, retiming, sequential circuit optimization, finite-state machine verification, and technology mapping for sequential circuits. SIS also supports asynchronous circuit synthesis and provides a framework for testing and comparing various algorithms. The paper provides an overview of SIS, detailing its input specification, state transition graph manipulation, logic optimization, verification algorithms, and synthesis for programmable gate arrays. An example is provided to illustrate the design process using SIS.SIS is an interactive tool for the synthesis and optimization of sequential circuits, designed to explore a larger solution space compared to traditional methods. It supports various input specifications, including state transition tables, signal transition graphs, and logic-level descriptions. SIS integrates multiple algorithms and techniques, allowing users to choose among different methods at each stage of the process. The system is built on top of MISII and includes enhancements for combinational optimization, such as improved performance optimization, storage and use of external don't cares, and faster divisor extraction. New sequential techniques include state minimization, state assignment, retiming, sequential circuit optimization, finite-state machine verification, and technology mapping for sequential circuits. SIS also supports asynchronous circuit synthesis and provides a framework for testing and comparing various algorithms. The paper provides an overview of SIS, detailing its input specification, state transition graph manipulation, logic optimization, verification algorithms, and synthesis for programmable gate arrays. An example is provided to illustrate the design process using SIS.