Signal crosstalk in a flip-chip quantum processor

Signal crosstalk in a flip-chip quantum processor

March 4, 2024 | Sandoko Kosen, Hang-Xi Li, Marcus Rommel, Robert Rehammar, Marco Caputo, Leif Grönberg, Jorge Fernández-Pendás, Anton Frisk Kockum, Janka Biznárová, Liangyu Chen, Christian Krizan, Andreas Nylander, Amr Osman, Anita Fadavi Roudsari, Daryoush Shiri, Giovanna Tancredi, Joonas Govenius, Jonas Bylander
The paper presents the design and characterization of a packaged flip-chip superconducting quantum processor with low signal crosstalk, crucial for maintaining high performance in large-scale quantum computing. The processor consists of 25 qubits and is designed with a repeating signal-line routing pattern to support scalability. The authors report on-resonant crosstalk for capacitively coupled qubit-drive lines (xy-lines) of better than −27 dB (average −37 dB) and direct-current flux crosstalk for inductively coupled magnetic-flux-drive lines (z-lines) of less than 0.13% (average 0.05%). These levels are promising for further scaling up to larger numbers of qubits. The study discusses the implications of these results for the design of low-crosstalk, on-chip signal delivery architectures, including the use of shielding tunnel structures and the influence of qubit separation on crosstalk levels. The results show a decreasing trend in crosstalk with increasing qubit separation, which is favorable for scaling. The paper also provides numerical estimates for the single-qubit gate error due to crosstalk in various scenarios and discusses the impact of crosstalk on gate fidelities.The paper presents the design and characterization of a packaged flip-chip superconducting quantum processor with low signal crosstalk, crucial for maintaining high performance in large-scale quantum computing. The processor consists of 25 qubits and is designed with a repeating signal-line routing pattern to support scalability. The authors report on-resonant crosstalk for capacitively coupled qubit-drive lines (xy-lines) of better than −27 dB (average −37 dB) and direct-current flux crosstalk for inductively coupled magnetic-flux-drive lines (z-lines) of less than 0.13% (average 0.05%). These levels are promising for further scaling up to larger numbers of qubits. The study discusses the implications of these results for the design of low-crosstalk, on-chip signal delivery architectures, including the use of shielding tunnel structures and the influence of qubit separation on crosstalk levels. The results show a decreasing trend in crosstalk with increasing qubit separation, which is favorable for scaling. The paper also provides numerical estimates for the single-qubit gate error due to crosstalk in various scenarios and discusses the impact of crosstalk on gate fidelities.
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