This article presents the development of steep-slope vertical-transport transistors (VTFETs) based on sub-5 nm van der Waals (vdW) heterostructures. The proposed device, called TS-VTFET, integrates a gate-controllable vdW heterojunction with a metal-filamentary threshold switch (TS), enabling a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The TS-VTFETs exhibit a current modulation ratio exceeding 1×10⁸ and an average sub-60 mV/dec subthreshold swing (SS) over six decades of drain current. These results demonstrate the potential of the TS-VTFETs to address the performance degradation and downscaling challenges faced by conventional planar FETs. The TS-VTFETs are fabricated using a combination of 2D materials, including MoS₂ and MoTe₂, and a TS cell based on Ag/TaOₓ/Ag. The TS cell enables abrupt resistance switching, which, when combined with the gate voltage-modulated conduction transition of the MoS₂/MoTe₂ heterojunction, results in a sub-5 nm transport channel and sub-60 mV/dec SS. The device shows excellent reliability, with strong voltage-cycling and DC-voltage stressing characteristics, making it suitable for practical applications. The TS-VTFETs outperform previously reported VTFETs in terms of sub-thermionic switching and low-power operation. They also demonstrate a high ON-OFF current ratio and low leakage current, making them promising candidates for future ultra-scaled and low-power digital logic devices. The device is fabricated using a dry transfer method and is compatible with the back-end-of-line (BEOL) process, which is beneficial for future low-energy electronic device manufacturing. The results show that the TS-VTFETs have excellent performance metrics, including a sub-thermionic SS down to -2.7 mV/dec at room temperature and a competitive sub-60 mV/dec region over six decades of drain current. These findings highlight the potential of vdW heterostructure-based VTFETs for next-generation ultra-scaled and low-power digital logic device technology.This article presents the development of steep-slope vertical-transport transistors (VTFETs) based on sub-5 nm van der Waals (vdW) heterostructures. The proposed device, called TS-VTFET, integrates a gate-controllable vdW heterojunction with a metal-filamentary threshold switch (TS), enabling a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The TS-VTFETs exhibit a current modulation ratio exceeding 1×10⁸ and an average sub-60 mV/dec subthreshold swing (SS) over six decades of drain current. These results demonstrate the potential of the TS-VTFETs to address the performance degradation and downscaling challenges faced by conventional planar FETs. The TS-VTFETs are fabricated using a combination of 2D materials, including MoS₂ and MoTe₂, and a TS cell based on Ag/TaOₓ/Ag. The TS cell enables abrupt resistance switching, which, when combined with the gate voltage-modulated conduction transition of the MoS₂/MoTe₂ heterojunction, results in a sub-5 nm transport channel and sub-60 mV/dec SS. The device shows excellent reliability, with strong voltage-cycling and DC-voltage stressing characteristics, making it suitable for practical applications. The TS-VTFETs outperform previously reported VTFETs in terms of sub-thermionic switching and low-power operation. They also demonstrate a high ON-OFF current ratio and low leakage current, making them promising candidates for future ultra-scaled and low-power digital logic devices. The device is fabricated using a dry transfer method and is compatible with the back-end-of-line (BEOL) process, which is beneficial for future low-energy electronic device manufacturing. The results show that the TS-VTFETs have excellent performance metrics, including a sub-thermionic SS down to -2.7 mV/dec at room temperature and a competitive sub-60 mV/dec region over six decades of drain current. These findings highlight the potential of vdW heterostructure-based VTFETs for next-generation ultra-scaled and low-power digital logic device technology.