This paper presents the development of steep-slope vertical-transport transistors (VTFETs) using sub-5 nm van der Waals (vdW) heterostructures. The researchers combined a gate-controllable van der Waals heterojunction with a metal-filamentary threshold switch (TS) to create VTFETs with a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The integrated TS-VTFETs exhibited efficient current switching behaviors, with a current modulation ratio exceeding 1 × 10^8 and an average sub-60 mV/dec subthreshold swing over 6 decades of drain current. The proposed TS-VTFETs offer excellent area- and energy-efficiency, addressing the performance degradation and downscaling challenges faced by conventional logic transistor technologies. The device's reliability was also systematically investigated, demonstrating strong voltage-cycling and DC-voltage stressing characteristics suitable for practical applications. The results provide a promising concept for future energy- and area-efficient vertical logic transistors.This paper presents the development of steep-slope vertical-transport transistors (VTFETs) using sub-5 nm van der Waals (vdW) heterostructures. The researchers combined a gate-controllable van der Waals heterojunction with a metal-filamentary threshold switch (TS) to create VTFETs with a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The integrated TS-VTFETs exhibited efficient current switching behaviors, with a current modulation ratio exceeding 1 × 10^8 and an average sub-60 mV/dec subthreshold swing over 6 decades of drain current. The proposed TS-VTFETs offer excellent area- and energy-efficiency, addressing the performance degradation and downscaling challenges faced by conventional logic transistor technologies. The device's reliability was also systematically investigated, demonstrating strong voltage-cycling and DC-voltage stressing characteristics suitable for practical applications. The results provide a promising concept for future energy- and area-efficient vertical logic transistors.