This article reports the monolithic three-dimensional (3D) integration of indium oxide (In₂O₃) thin-film transistors (TFTs) on a silicon/silicon dioxide (Si/SiO₂) substrate at room temperature. The approach is compatible with complementary metal–oxide–semiconductor (CMOS) processes, allowing for the stacking of ten n-channel In₂O₃ TFTs in various architectures, including bottom-gate (BG), top-gate (TG), and dual-gate (DG) transistors. The dual-gate devices exhibit enhanced electrical performance, with a maximum field-effect mobility of 15 cm² V⁻¹ s⁻¹, a subthreshold swing of 0.4 V dec⁻¹, and a current on/off ratio of 10⁶. Unipolar inverter circuits were created using these 3D-integrated In₂O₃ TFTs, achieving a signal gain of around 50 and wide noise margins. The study also discusses the potential for creating vertical interconnects to improve the integration process and addresses device reliability and scalability. The results demonstrate the feasibility of 3D monolithic integration for high-density, energy-efficient, and low-cost integrated circuits.This article reports the monolithic three-dimensional (3D) integration of indium oxide (In₂O₃) thin-film transistors (TFTs) on a silicon/silicon dioxide (Si/SiO₂) substrate at room temperature. The approach is compatible with complementary metal–oxide–semiconductor (CMOS) processes, allowing for the stacking of ten n-channel In₂O₃ TFTs in various architectures, including bottom-gate (BG), top-gate (TG), and dual-gate (DG) transistors. The dual-gate devices exhibit enhanced electrical performance, with a maximum field-effect mobility of 15 cm² V⁻¹ s⁻¹, a subthreshold swing of 0.4 V dec⁻¹, and a current on/off ratio of 10⁶. Unipolar inverter circuits were created using these 3D-integrated In₂O₃ TFTs, achieving a signal gain of around 50 and wide noise margins. The study also discusses the potential for creating vertical interconnects to improve the integration process and addresses device reliability and scalability. The results demonstrate the feasibility of 3D monolithic integration for high-density, energy-efficient, and low-cost integrated circuits.