Toward Low-latency Iterative Decoding of QLDPC Codes Under Circuit-Level Noise

Toward Low-latency Iterative Decoding of QLDPC Codes Under Circuit-Level Noise

27 Mar 2024 | Anqi Gong, Sebastian Cammerer, and Joseph M. Renes
This paper introduces a sliding window decoder based on belief propagation (BP) with guided decimation (GDG) for decoding quantum low-density parity-check (QLDPC) codes under circuit-level noise. The GDG decoder improves upon BP with guided decimation (BPGD) by incorporating guessing strategies to enhance convergence speed and reduce logical error rates. The decoder is applied to bivariate bicycle (BB) codes, achieving performance comparable to BP with an additional ordered-statistics decoding (OSD) post-processing stage (BP+OSD) and combination-sweep of order 10. For a window size of three syndrome cycles, a multi-threaded CPU implementation of GDG achieves a worst-case decoding latency of 3ms per window for the [[144,12,12]] code. The paper discusses the challenges of decoding QLDPC codes under circuit-level noise, including the presence of short loops and symmetric trapping sets that can hinder decoding performance. To address these issues, the paper proposes the use of sliding window decoding, which allows for efficient decoding by processing a small number of recent syndrome measurements at a time. The GDG decoder is designed to handle the unique characteristics of circuit-level noise, including the presence of multiple fault mechanisms that can trigger different detectors. The GDG decoder uses a combination of BP and guessing strategies to improve convergence speed and reduce logical error rates. The decoder employs a decision tree to select and decimate variable nodes (VNs) based on their posterior log-likelihood ratios (LLRs). The decision tree includes main branches, side branches, and tree branches that explore different decimation values to find the most probable error pattern. The paper also discusses the performance of the GDG decoder on different code lengths and error rates, showing that it achieves excellent logical error rates for physical error rates up to 0.002. The paper concludes that the GDG decoder is a promising approach for decoding QLDPC codes under circuit-level noise, with the potential to be implemented on specialized hardware to further improve performance. The decoder is designed for syndrome decoding, not codeword decoding, and the paper suggests that similar VN selection rules could be developed for codeword decoding based on the history of sign and LLR values. The paper also highlights the importance of peeling steps to prevent the decoder from wasting decision steps on apparently decidable VNs.This paper introduces a sliding window decoder based on belief propagation (BP) with guided decimation (GDG) for decoding quantum low-density parity-check (QLDPC) codes under circuit-level noise. The GDG decoder improves upon BP with guided decimation (BPGD) by incorporating guessing strategies to enhance convergence speed and reduce logical error rates. The decoder is applied to bivariate bicycle (BB) codes, achieving performance comparable to BP with an additional ordered-statistics decoding (OSD) post-processing stage (BP+OSD) and combination-sweep of order 10. For a window size of three syndrome cycles, a multi-threaded CPU implementation of GDG achieves a worst-case decoding latency of 3ms per window for the [[144,12,12]] code. The paper discusses the challenges of decoding QLDPC codes under circuit-level noise, including the presence of short loops and symmetric trapping sets that can hinder decoding performance. To address these issues, the paper proposes the use of sliding window decoding, which allows for efficient decoding by processing a small number of recent syndrome measurements at a time. The GDG decoder is designed to handle the unique characteristics of circuit-level noise, including the presence of multiple fault mechanisms that can trigger different detectors. The GDG decoder uses a combination of BP and guessing strategies to improve convergence speed and reduce logical error rates. The decoder employs a decision tree to select and decimate variable nodes (VNs) based on their posterior log-likelihood ratios (LLRs). The decision tree includes main branches, side branches, and tree branches that explore different decimation values to find the most probable error pattern. The paper also discusses the performance of the GDG decoder on different code lengths and error rates, showing that it achieves excellent logical error rates for physical error rates up to 0.002. The paper concludes that the GDG decoder is a promising approach for decoding QLDPC codes under circuit-level noise, with the potential to be implemented on specialized hardware to further improve performance. The decoder is designed for syndrome decoding, not codeword decoding, and the paper suggests that similar VN selection rules could be developed for codeword decoding based on the history of sign and LLR values. The paper also highlights the importance of peeling steps to prevent the decoder from wasting decision steps on apparently decidable VNs.
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[slides and audio] Toward Low-latency Iterative Decoding of QLDPC Codes Under Circuit-Level Noise