This paper introduces VeriAssist, an LLM-powered assistant for Verilog RTL design that enables self-correction and self-verification. Traditional RTL design workflows require manual coding by experts, which is time-consuming and error-prone. VeriAssist leverages LLMs to generate high-quality RTL code with corresponding test benches. It uses an automatic prompting system and integrates RTL simulators in the code generation loop to self-correct and self-verify the generated code. The process involves generating initial RTL code, self-verification through test cases, and self-correction based on simulation results. VeriAssist improves the quality of generated code by utilizing LLMs' multi-turn interaction and chain-of-thought reasoning capabilities. Evaluations on various benchmark suites show that VeriAssist significantly improves both syntax and functionality correctness over existing LLM implementations, reducing the need for human intervention and making RTL design more accessible to novices. The design of VeriAssist includes constructing an initial prompt from the problem description, followed by prompts for self-verification and self-correction. The system is integrated with a simulator to facilitate the prompt-generate-feedback-revise loop. VeriAssist's workflow includes initial prompt preparation, RTL code generation, syntactical verification, functional verification, and iterative design and refinement. The results show that VeriAssist outperforms existing approaches in RTL code generation, achieving higher functionality pass rates and better performance compared to designer reference code. The study also highlights the importance of test bench generation in improving RTL code quality and the challenges of generating high-quality test benches for RTL design. Future work will focus on integrating synthesis results into the feedback loop of VeriAssist to further improve the performance of generated RTL code.This paper introduces VeriAssist, an LLM-powered assistant for Verilog RTL design that enables self-correction and self-verification. Traditional RTL design workflows require manual coding by experts, which is time-consuming and error-prone. VeriAssist leverages LLMs to generate high-quality RTL code with corresponding test benches. It uses an automatic prompting system and integrates RTL simulators in the code generation loop to self-correct and self-verify the generated code. The process involves generating initial RTL code, self-verification through test cases, and self-correction based on simulation results. VeriAssist improves the quality of generated code by utilizing LLMs' multi-turn interaction and chain-of-thought reasoning capabilities. Evaluations on various benchmark suites show that VeriAssist significantly improves both syntax and functionality correctness over existing LLM implementations, reducing the need for human intervention and making RTL design more accessible to novices. The design of VeriAssist includes constructing an initial prompt from the problem description, followed by prompts for self-verification and self-correction. The system is integrated with a simulator to facilitate the prompt-generate-feedback-revise loop. VeriAssist's workflow includes initial prompt preparation, RTL code generation, syntactical verification, functional verification, and iterative design and refinement. The results show that VeriAssist outperforms existing approaches in RTL code generation, achieving higher functionality pass rates and better performance compared to designer reference code. The study also highlights the importance of test bench generation in improving RTL code quality and the challenges of generating high-quality test benches for RTL design. Future work will focus on integrating synthesis results into the feedback loop of VeriAssist to further improve the performance of generated RTL code.