Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction

Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction

31 May 2024 | Hanxian Huang, Zhenghan Lin, Zixuan Wang, Xin Chen, Ke Ding, Jishen Zhao
The paper introduces VeriAssist, an LLM-powered assistant designed to generate high-quality Register-Transfer Level (RTL) code with minimal human intervention. Traditional RTL design workflows are time-consuming and error-prone, requiring manual coding. VeriAssist addresses these challenges by leveraging Large Language Models (LLMs) to generate RTL code and corresponding test benches. The system employs a multi-turn generation process, including initial prompt preparation, RTL code generation, syntactical verification, functional verification, and iterative design refinement. VeriAssist integrates an automatic prompting system and an RTL simulator to enable self-verification and self-correction. The evaluation using various benchmark suites shows that VeriAssist significantly improves both syntax and functionality correctness, achieving a pass@5 score of 72.3%. The system also demonstrates robustness across different prompt variants and outperforms existing LLM implementations in generating high-quality RTL code. Future work will focus on integrating synthesis results and improving test bench generation.The paper introduces VeriAssist, an LLM-powered assistant designed to generate high-quality Register-Transfer Level (RTL) code with minimal human intervention. Traditional RTL design workflows are time-consuming and error-prone, requiring manual coding. VeriAssist addresses these challenges by leveraging Large Language Models (LLMs) to generate RTL code and corresponding test benches. The system employs a multi-turn generation process, including initial prompt preparation, RTL code generation, syntactical verification, functional verification, and iterative design refinement. VeriAssist integrates an automatic prompting system and an RTL simulator to enable self-verification and self-correction. The evaluation using various benchmark suites shows that VeriAssist significantly improves both syntax and functionality correctness, achieving a pass@5 score of 72.3%. The system also demonstrates robustness across different prompt variants and outperforms existing LLM implementations in generating high-quality RTL code. Future work will focus on integrating synthesis results and improving test bench generation.
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Understanding Towards LLM-Powered Verilog RTL Assistant%3A Self-Verification and Self-Correction