The paper introduces the Transactional Locking II (TL2) algorithm, a software transactional memory (STM) algorithm that combines commit-time locking with a novel global version-clock validation technique. TL2 improves upon existing STMs by: 1. **Seamless Integration**: It integrates seamlessly with any system memory lifecycle, including those using malloc/free. 2. **Efficient Execution**: Unlike other lock-based STMs, it avoids unsafe execution periods by ensuring user code operates only on consistent memory states. 3. **Performance**: In high-performance benchmarks, TL2 delivers comparable or better performance compared to all former STM algorithms, both lock-based and non-blocking. It is ten times faster than a single lock. The authors argue that these characteristics make TL2 a viable candidate for deployment of transactional memory before hardware support becomes available. The paper also discusses the broader context of transactional memory, emphasizing the need for mechanical methods to transform sequential or coarse-grained lock-based code into concurrent code, and the challenges and trends in STM design.The paper introduces the Transactional Locking II (TL2) algorithm, a software transactional memory (STM) algorithm that combines commit-time locking with a novel global version-clock validation technique. TL2 improves upon existing STMs by: 1. **Seamless Integration**: It integrates seamlessly with any system memory lifecycle, including those using malloc/free. 2. **Efficient Execution**: Unlike other lock-based STMs, it avoids unsafe execution periods by ensuring user code operates only on consistent memory states. 3. **Performance**: In high-performance benchmarks, TL2 delivers comparable or better performance compared to all former STM algorithms, both lock-based and non-blocking. It is ten times faster than a single lock. The authors argue that these characteristics make TL2 a viable candidate for deployment of transactional memory before hardware support becomes available. The paper also discusses the broader context of transactional memory, emphasizing the need for mechanical methods to transform sequential or coarse-grained lock-based code into concurrent code, and the challenges and trends in STM design.