The paper introduces VPR, a new FPGA CAD tool designed for flexible placement and routing of circuits on various FPGA architectures. VPR outperforms existing tools in minimizing routing area and has been benchmarked on a set of large circuits to facilitate future comparisons with other FPGA place and route tools. The tool is publicly available and has been used in multiple research projects worldwide. The paper details the placement and routing algorithms, including the simulated annealing algorithm for placement and the Pathfinder negotiated congestion algorithm for routing. Experimental results show that VPR requires fewer tracks compared to other tools, both when performing global routing and when combining global and detailed routing. The tool is also flexible enough to handle different FPGA architectures and can be used in various FPGA architectural studies. Future improvements include support for buffered and segmented routing structures, a timing analyzer, and timing-driven routing.The paper introduces VPR, a new FPGA CAD tool designed for flexible placement and routing of circuits on various FPGA architectures. VPR outperforms existing tools in minimizing routing area and has been benchmarked on a set of large circuits to facilitate future comparisons with other FPGA place and route tools. The tool is publicly available and has been used in multiple research projects worldwide. The paper details the placement and routing algorithms, including the simulated annealing algorithm for placement and the Pathfinder negotiated congestion algorithm for routing. Experimental results show that VPR requires fewer tracks compared to other tools, both when performing global routing and when combining global and detailed routing. The tool is also flexible enough to handle different FPGA architectures and can be used in various FPGA architectural studies. Future improvements include support for buffered and segmented routing structures, a timing analyzer, and timing-driven routing.