VPR is a new FPGA CAD tool that outperforms existing tools in routing area minimization. It uses simulated annealing for placement and a modified Pathfinder algorithm for routing. VPR is flexible, supporting various FPGA architectures and is publicly available. It includes a netlist translator, VPACK, for converting circuits into VPR's format. VPR's placement algorithm uses a linear congestion cost function, which improves routing efficiency. The routing algorithm adjusts to channel widths and routing resource usage, ensuring efficient routing. Experimental results show VPR requires fewer tracks than other tools, especially for large circuits. VPR's placement and routing are compared against other tools, demonstrating its effectiveness. VPR is also capable of handling large benchmark circuits, and it is designed to be flexible for future FPGA research. Future improvements include buffered and segmented routing, a timing analyzer, and timing-driven routing. VPR is available for research and is expected to be used in future FPGA CAD tool comparisons.VPR is a new FPGA CAD tool that outperforms existing tools in routing area minimization. It uses simulated annealing for placement and a modified Pathfinder algorithm for routing. VPR is flexible, supporting various FPGA architectures and is publicly available. It includes a netlist translator, VPACK, for converting circuits into VPR's format. VPR's placement algorithm uses a linear congestion cost function, which improves routing efficiency. The routing algorithm adjusts to channel widths and routing resource usage, ensuring efficient routing. Experimental results show VPR requires fewer tracks than other tools, especially for large circuits. VPR's placement and routing are compared against other tools, demonstrating its effectiveness. VPR is also capable of handling large benchmark circuits, and it is designed to be flexible for future FPGA research. Future improvements include buffered and segmented routing, a timing analyzer, and timing-driven routing. VPR is available for research and is expected to be used in future FPGA CAD tool comparisons.